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[src/trunk]: src/sys/arch Add support Marvell Dove.
details: https://anonhg.NetBSD.org/src/rev/36c25bc3c625
branches: trunk
changeset: 350195:36c25bc3c625
user: kiyohara <kiyohara%NetBSD.org@localhost>
date: Sat Jan 07 16:19:28 2017 +0000
description:
Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.
diffstat:
sys/arch/arm/arm/cpufunc_asm_pj4b.S | 4 +-
sys/arch/arm/marvell/armadaxp.c | 63 ++-
sys/arch/arm/marvell/armadaxpvar.h | 6 +-
sys/arch/arm/marvell/dove.c | 562 ++++++++++++++++++++++++++++
sys/arch/arm/marvell/dovereg.h | 289 ++++++++++++++
sys/arch/arm/marvell/files.marvell | 14 +-
sys/arch/arm/marvell/kirkwood.c | 23 +-
sys/arch/arm/marvell/mv78xx0.c | 21 +-
sys/arch/arm/marvell/mvsoc.c | 132 ++++++-
sys/arch/arm/marvell/mvsoc_sdhc.c | 107 +++++
sys/arch/arm/marvell/mvsoc_space.c | 43 ++-
sys/arch/arm/marvell/mvsocpmu.c | 203 ++++++++++
sys/arch/arm/marvell/mvsocpmuvar.h | 48 ++
sys/arch/arm/marvell/mvsocreg.h | 19 +-
sys/arch/arm/marvell/mvsocvar.h | 33 +-
sys/arch/arm/marvell/orion.c | 19 +-
sys/arch/evbarm/armadaxp/armadaxp_machdep.c | 44 +-
sys/arch/evbarm/marvell/marvell_machdep.c | 117 ++--
sys/arch/evbarm/marvell/marvellreg.h | 3 +-
19 files changed, 1585 insertions(+), 165 deletions(-)
diffs (truncated from 2389 to 300 lines):
diff -r 2ee8e81e9a7f -r 36c25bc3c625 sys/arch/arm/arm/cpufunc_asm_pj4b.S
--- a/sys/arch/arm/arm/cpufunc_asm_pj4b.S Sat Jan 07 15:47:33 2017 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_pj4b.S Sat Jan 07 16:19:28 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.12 2017/01/07 15:22:11 kiyohara Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.13 2017/01/07 16:19:28 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -102,6 +102,7 @@
RET
END(pj4b_config)
+#ifdef AURORA_IO_CACHE_COHERENCY
/* LINTSTUB: void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); */
ENTRY_NP(pj4b_io_coherency_barrier)
movw r0, #:lower16:_C_LABEL(armadaxp_l2_barrier_reg)
@@ -120,3 +121,4 @@
STRONG_ALIAS(pj4b_dcache_cfu_wbinv_range, pj4b_io_coherency_barrier)
STRONG_ALIAS(pj4b_dcache_cfu_inv_range, pj4b_io_coherency_barrier)
STRONG_ALIAS(pj4b_dcache_cfu_wb_range, pj4b_io_coherency_barrier)
+#endif
diff -r 2ee8e81e9a7f -r 36c25bc3c625 sys/arch/arm/marvell/armadaxp.c
--- a/sys/arch/arm/marvell/armadaxp.c Sat Jan 07 15:47:33 2017 +0000
+++ b/sys/arch/arm/marvell/armadaxp.c Sat Jan 07 16:19:28 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.16 2017/01/07 16:19:28 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.15 2015/06/03 02:53:19 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.16 2017/01/07 16:19:28 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -90,7 +90,6 @@
vaddr_t misc_base;
vaddr_t armadaxp_l2_barrier_reg;
-extern void (*mvsoc_intr_init)(void);
static void armadaxp_intr_init(void);
static void armadaxp_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
@@ -111,6 +110,17 @@
int, char*, size_t);
static int armadaxp_err_pic_pending_irqs(struct pic_softc *);
+static void armadaxp_getclks(void);
+static void armada370_getclks(void);
+static int armadaxp_clkgating(struct marvell_attach_args *);
+
+static int armadaxp_l2_init(bus_addr_t);
+static paddr_t armadaxp_sdcache_wbalign_base(vaddr_t, paddr_t, psize_t);
+static paddr_t armadaxp_sdcache_wbalign_end(vaddr_t, paddr_t, psize_t);
+#ifdef AURORA_IO_CACHE_COHERENCY
+static void armadaxp_io_coherency_init(void);
+#endif
+
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
@@ -511,13 +521,13 @@
};
/*
- * armadaxp_intr_bootstrap:
+ * armadaxp_bootstrap:
*
- * Initialize the rest of the interrupt subsystem, making it
+ * Initialize the rest of the Armada XP dependencies, making it
* ready to handle interrupts from devices.
*/
void
-armadaxp_intr_bootstrap(bus_addr_t pbase)
+armadaxp_bootstrap(vaddr_t vbase, bus_addr_t pbase)
{
int i;
@@ -534,6 +544,35 @@
MPIC_WRITE(ARMADAXP_MLMB_MPIC_ICE, i);
mvsoc_intr_init = armadaxp_intr_init;
+
+ mvsoc_clkgating = armadaxp_clkgating;
+
+ misc_base = vbase + ARMADAXP_MISC_BASE;
+ switch (mvsoc_model()) {
+ case MARVELL_ARMADAXP_MV78130:
+ case MARVELL_ARMADAXP_MV78160:
+ case MARVELL_ARMADAXP_MV78230:
+ case MARVELL_ARMADAXP_MV78260:
+ case MARVELL_ARMADAXP_MV78460:
+ armadaxp_getclks();
+ break;
+
+ case MARVELL_ARMADA370_MV6707:
+ case MARVELL_ARMADA370_MV6710:
+ case MARVELL_ARMADA370_MV6W11:
+ armada370_getclks();
+ break;
+ }
+
+#ifdef L2CACHE_ENABLE
+ /* Initialize L2 Cache */
+ armadaxp_l2_init(pbase);
+#endif
+
+#ifdef AURORA_IO_CACHE_COHERENCY
+ /* Initialize cache coherency */
+ armadaxp_io_coherency_init();
+#endif
}
static void
@@ -744,7 +783,7 @@
* Clock functions
*/
-void
+static void
armadaxp_getclks(void)
{
uint64_t sar_reg;
@@ -789,7 +828,7 @@
curcpu()->ci_data.cpu_cc_freq = mvPclk;
}
-void
+static void
armada370_getclks(void)
{
uint32_t sar;
@@ -834,7 +873,7 @@
* L2 Cache initialization
*/
-int
+static int
armadaxp_l2_init(bus_addr_t pbase)
{
u_int32_t reg;
@@ -1030,7 +1069,8 @@
__asm__ __volatile__("dsb");
}
-void
+#ifdef AURORA_IO_CACHE_COHERENCY
+static void
armadaxp_io_coherency_init(void)
{
uint32_t reg;
@@ -1057,8 +1097,9 @@
/* Mark as enabled */
iocc_state = 1;
}
+#endif
-int
+static int
armadaxp_clkgating(struct marvell_attach_args *mva)
{
uint32_t val;
diff -r 2ee8e81e9a7f -r 36c25bc3c625 sys/arch/arm/marvell/armadaxpvar.h
--- a/sys/arch/arm/marvell/armadaxpvar.h Sat Jan 07 15:47:33 2017 +0000
+++ b/sys/arch/arm/marvell/armadaxpvar.h Sat Jan 07 16:19:28 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxpvar.h,v 1.2 2015/06/03 02:53:19 hsuenaga Exp $ */
+/* $NetBSD: armadaxpvar.h,v 1.3 2017/01/07 16:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2015 SUENAGA Hiroki
* All rights reserved.
@@ -29,10 +29,6 @@
#include <arm/marvell/mvsocvar.h>
#include <machine/bus_defs.h>
-/* device initalization */
-extern void armadaxp_io_coherency_init(void);
-extern int armadaxp_l2_init(bus_addr_t);
-
/* l2cache maintanance */
extern void armadaxp_sdcache_inv_all(void);
extern void armadaxp_sdcache_wb_all(void);
diff -r 2ee8e81e9a7f -r 36c25bc3c625 sys/arch/arm/marvell/dove.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/dove.c Sat Jan 07 16:19:28 2017 +0000
@@ -0,0 +1,562 @@
+/* $NetBSD: dove.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $ */
+/*
+ * Copyright (c) 2016 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dove.c,v 1.1 2017/01/07 16:19:28 kiyohara Exp $");
+
+#define _INTR_PRIVATE
+
+#include "mvsocgpp.h"
+#include "mvsocpmu.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+
+#include <machine/intr.h>
+
+#include <arm/cpufunc.h>
+#include <arm/pic/picvar.h>
+#include <arm/pic/picvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsocpmuvar.h>
+#include <arm/marvell/dovereg.h>
+
+#include <dev/marvell/marvellreg.h>
+
+
+#define read_dbreg read_mlmbreg
+#define write_dbreg write_mlmbreg
+#if NMVSOCPMU > 0
+#define READ_PMUREG(sc, o) \
+ bus_space_read_4((sc)->sc_iot, (sc)->sc_pmch, (o))
+#define WRITE_PMUREG(sc, o, v) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_pmch, (o), (v))
+#else
+vaddr_t pmu_base = -1;
+#define READ_PMUREG(sc, o) (*(volatile uint32_t *)(pmu_base + (o)))
+#endif
+
+static void dove_intr_init(void);
+
+static void dove_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void dove_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static void dove_pic_establish_irq(struct pic_softc *, struct intrsource *);
+static void dove_pic_source_name(struct pic_softc *, int, char *, size_t);
+
+static int dove_find_pending_irqs(void);
+
+static void dove_getclks(bus_addr_t);
+static int dove_clkgating(struct marvell_attach_args *);
+
+#if NMVSOCPMU > 0
+struct dove_pmu_softc {
+ struct mvsocpmu_softc sc_mvsocpmu_sc;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_pmch; /* Power Management Core handler */
+ bus_space_handle_t sc_pmh; /* Power Management handler */
+
+ int sc_xpratio;
+ int sc_dpratio;
+};
+static int dove_pmu_match(device_t, struct cfdata *, void *);
+static void dove_pmu_attach(device_t, device_t, void *);
+static int dove_pmu_intr(void *);
+static int dove_tm_val2uc(int);
+static int dove_tm_uc2val(int);
+static int dove_dfs_slow(struct dove_pmu_softc *, bool);
+
+CFATTACH_DECL_NEW(mvsocpmu, sizeof(struct dove_pmu_softc),
+ dove_pmu_match, dove_pmu_attach, NULL, NULL);
+#endif
+
+
+static const char * const sources[64] = {
+ "Bridge(0)", "Host2CPUDoorbell(1)","CPU2HostDoorbell(2)","NF(3)",
+ "PDMA(4)", "SPI1(5)", "SPI0(6)", "UART0(7)",
+ "UART1(8)", "UART2(9)", "UART3(10)", "TWSI(11)",
+ "GPIO7_0(12)", "GPIO15_8(13)", "GPIO23_16(14)", "PEX0_Err(15)",
+ "PEX0_INT(16)", "PEX1_Err(17)", "PEX1_INT(18)", "Audio0_INT(19)",
+ "Audio0_Err(20)", "Audio1_INT(21)", "Audio1_Err(22)", "USBBr(23)",
+ "USB0Cnt(24)", "USB1Cnt(25)", "GbERx(26)", "GbETx(27)",
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