[src/trunk]: src/sys/arch/aarch64/include Correct definitions for TCR.

[maya <maya%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c909614c2aab
branches:  trunk
changeset: 350683:c909614c2aab
user:      maya <maya%NetBSD.org@localhost>
date:      Mon Jan 16 10:15:42 2017 +0000

description:
Correct definitions for TCR.

Values from ARM Cortex A-53 MPCore Processor Technical Reference Manual
4.3.48. Translation Control Register, EL1

diffstat:

 sys/arch/aarch64/include/pte.h |  6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diffs (20 lines):

diff -r 7826c40966fb -r c909614c2aab sys/arch/aarch64/include/pte.h
--- a/sys/arch/aarch64/include/pte.h    Mon Jan 16 09:58:04 2017 +0000
+++ b/sys/arch/aarch64/include/pte.h    Mon Jan 16 10:15:42 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.1 2014/08/10 05:47:38 matt Exp $ */
+/* $NetBSD: pte.h,v 1.2 2017/01/16 10:15:42 maya Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -107,8 +107,8 @@
 #define TCR_T1SZ               __BITS(21,16)   // Size offset for TTBR1_EL1
 #define TCR_TG0                        __BITS(15,14)
 #define TCR_SH0                        __BITS(13,12)
-#define TCR_ORGN1              __BITS(11,10)
-#define TCR_IRGN1              __BITS(9,8)
+#define TCR_ORGN0              __BITS(11,10)
+#define TCR_IRGN0              __BITS(9,8)
 #define TCR_EPD0               __BIT(7)        // Walk Disable for TTBR0
 #define TCR_T0SZ               __BITS(5,0)     // Size offset for TTBR0_EL1