[src/trunk]: src/sys/arch/arm/nvidia add USB2_TRK and HSIC_TRK clocks

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1e7860dcc85c
branches:  trunk
changeset: 356393:1e7860dcc85c
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Sep 22 10:54:44 2017 +0000

description:
add USB2_TRK and HSIC_TRK clocks

diffstat:

 sys/arch/arm/nvidia/tegra210_car.c    |   8 +++++-
 sys/arch/arm/nvidia/tegra210_carreg.h |  37 ++++++++++++++++++++++++++++++++++-
 2 files changed, 42 insertions(+), 3 deletions(-)

diffs (92 lines):

diff -r 7ea9ed383d86 -r 1e7860dcc85c sys/arch/arm/nvidia/tegra210_car.c
--- a/sys/arch/arm/nvidia/tegra210_car.c        Fri Sep 22 06:31:02 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_car.c        Fri Sep 22 10:54:44 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.5 2017/09/22 01:24:05 jmcneill Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.6 2017/09/22 10:54:44 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.5 2017/09/22 01:24:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.6 2017/09/22 10:54:44 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -536,6 +536,8 @@
                CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV),
        CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON",
                CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV),
+       CLK_DIV("USB2_HSIC_TRK", "CLK_M",
+               CAR_CLKSRC_USB2_HSIC_TRK_REG, CAR_CLKSRC_USB2_HSIC_TRK_DIV),
 
        CLK_GATE_L("UARTA", "DIV_UARTA", CAR_DEV_L_UARTA),
        CLK_GATE_L("UARTB", "DIV_UARTB", CAR_DEV_L_UARTB),
@@ -554,6 +556,8 @@
        CLK_GATE_U("XUSB_HOST", "XUSB_HOST_SRC", CAR_DEV_U_XUSB_HOST),
        CLK_GATE_W("XUSB_SS", "XUSB_SS_SRC", CAR_DEV_W_XUSB_SS),
        CLK_GATE_H("FUSE", "CLK_M", CAR_DEV_H_FUSE),
+       CLK_GATE_Y("USB2_TRK", "UBS2_HSIC_TRK", CAR_DEV_Y_USB2_TRK),
+       CLK_GATE_Y("HSIC_TRK", "USB2_HSIC_TRK", CAR_DEV_Y_HSIC_TRK),
 };
 
 struct tegra210_init_parent {
diff -r 7ea9ed383d86 -r 1e7860dcc85c sys/arch/arm/nvidia/tegra210_carreg.h
--- a/sys/arch/arm/nvidia/tegra210_carreg.h     Fri Sep 22 06:31:02 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra210_carreg.h     Fri Sep 22 10:54:44 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.3 2017/09/22 01:24:31 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.4 2017/09/22 10:54:44 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -438,6 +438,38 @@
 #define CAR_DEV_X_ETR                  __BIT(3)
 #define CAR_DEV_X_SPARE                        __BIT(0)
 
+#define        CAR_DEV_Y_PLLP_OUT_CPU          __BIT(31)
+#define        CAR_DEV_Y_SOR_SAFE              __BIT(30)
+#define        CAR_DEV_Y_IQC1                  __BIT(29)
+#define        CAR_DEV_Y_IQC2                  __BIT(28)
+#define        CAR_DEV_Y_NVENC                 __BIT(27)
+#define        CAR_DEV_Y_ADSPNEON              __BIT(26)
+#define        CAR_DEV_Y_ADSPSCU               __BIT(25)
+#define        CAR_DEV_Y_ADSPWDT               __BIT(24)
+#define        CAR_DEV_Y_ADSPDBG               __BIT(23)
+#define        CAR_DEV_Y_ADSPPERIPH            __BIT(22)
+#define        CAR_DEV_Y_ADSPINTF              __BIT(21)
+#define        CAR_DEV_Y_UARTAPE               __BIT(20)
+#define        CAR_DEV_Y_QSPI                  __BIT(19)
+#define        CAR_DEV_Y_USB2_TRK              __BIT(18)
+#define        CAR_DEV_Y_HSIC_TRK              __BIT(17)
+#define        CAR_DEV_Y_VI_I2C                __BIT(16)
+#define        CAR_DEV_Y_DPAUX                 __BIT(15)
+#define        CAR_DEV_Y_TSECB                 __BIT(14)
+#define        CAR_DEV_Y_PEX_USB_UPHY          __BIT(13)
+#define        CAR_DEV_Y_SATA_USB_UPHY         __BIT(12)
+#define        CAR_DEV_Y_MAUD                  __BIT(10)
+#define        CAR_DEV_Y_MC_CCPA               __BIT(9)
+#define        CAR_DEV_Y_MC_CDPA               __BIT(8)
+#define        CAR_DEV_Y_ADSP                  __BIT(7)
+#define        CAR_DEV_Y_APE                   __BIT(6)
+#define        CAR_DEV_Y_DMIC3                 __BIT(5)
+#define        CAR_DEV_Y_AXIAP                 __BIT(4)
+#define        CAR_DEV_Y_NVJPG                 __BIT(3)
+#define        CAR_DEV_Y_NVDEC                 __BIT(2)
+#define        CAR_DEV_Y_SDMMC_LEGACY_TM       __BIT(1)
+#define        CAR_DEV_Y_SPARE1                __BIT(0)
+
 #define CAR_CCLKG_BURST_POLICY_REG     0x368
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE       __BITS(31,28)
 #define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE                  1
@@ -578,4 +610,7 @@
 #define CAR_CLKSRC_SOC_THERM_DDLL_SEL  __BITS(11,10)
 #define CAR_CLKSRC_SOC_THERM_DIV       __BITS(7,0)
 
+#define        CAR_CLKSRC_USB2_HSIC_TRK_REG    0x6cc
+#define        CAR_CLKSRC_USB2_HSIC_TRK_DIV    __BITS(7,0)
+
 #endif /* _ARM_TEGRA210_CARREG_H */