[src/trunk]: src/sys/dev/pci Lowercase for consistency. No functional change.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/589c3c4440e9
branches:  trunk
changeset: 352366:589c3c4440e9
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Mar 28 10:23:40 2017 +0000

description:
Lowercase for consistency. No functional change.

diffstat:

 sys/dev/pci/pcireg.h |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r a947e1a3d026 -r 589c3c4440e9 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Tue Mar 28 08:47:19 2017 +0000
+++ b/sys/dev/pci/pcireg.h      Tue Mar 28 10:23:40 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.122 2017/03/14 08:20:11 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.123 2017/03/28 10:23:40 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -653,7 +653,7 @@
                                         * (most significant bits) offset
                                         */
 #define        PCI_MSI_MDATA           0x8     /* Message Data Register offset */
-#define        PCI_MSI_MDATA64         0xC     /* 64-bit Message Data Register
+#define        PCI_MSI_MDATA64         0xc     /* 64-bit Message Data Register
                                         * offset
                                         */
 #define        PCI_MSI_MASK            0x10    /* Vector Mask register */
@@ -1259,7 +1259,7 @@
 #define          PCI_BRIDGE_PREFETCHMEM_64BITS(reg)    ((reg) & 0xf)
 
 #define PCI_BRIDGE_PREFETCHBASE32_REG  0x28
-#define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C
+#define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2c
 
 #define PCI_BRIDGE_IOHIGH_REG          0x30
 #define          PCI_BRIDGE_IOHIGH_BASE_SHIFT          0
@@ -1267,7 +1267,7 @@
 #define          PCI_BRIDGE_IOHIGH_BASE_MASK           0xffff
 #define          PCI_BRIDGE_IOHIGH_LIMIT_MASK          0xffff
 
-#define PCI_BRIDGE_CONTROL_REG         0x3C
+#define PCI_BRIDGE_CONTROL_REG         0x3c
 #define          PCI_BRIDGE_CONTROL_SHIFT              16
 #define          PCI_BRIDGE_CONTROL_MASK               0xffff
 #define   PCI_BRIDGE_CONTROL_PERE              (1 <<  0)