[src/trunk]: src/sys/dev/pci - Fix wm_set_ral():

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/72a7ac1ab791
branches:  trunk
changeset: 354702:72a7ac1ab791
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Jun 26 04:09:02 2017 +0000

description:
- Fix wm_set_ral():
 - Fix a bug that a RAL was written at incorrect address when the index number
   is more than 16 on 82544 and newer.
 - The layout of RAL on PCH* are different from others.
- Remove wrong comment.

diffstat:

 sys/dev/pci/if_wm.c    |  64 +++++++++++++++++++++++++++++++++++++++++--------
 sys/dev/pci/if_wmreg.h |  15 ++++++++---
 2 files changed, 64 insertions(+), 15 deletions(-)

diffs (128 lines):

diff -r 39aa2f9d6557 -r 72a7ac1ab791 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c       Mon Jun 26 04:03:34 2017 +0000
+++ b/sys/dev/pci/if_wm.c       Mon Jun 26 04:09:02 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wm.c,v 1.513 2017/06/26 04:03:34 msaitoh Exp $      */
+/*     $NetBSD: if_wm.c,v 1.514 2017/06/26 04:09:02 msaitoh Exp $      */
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -84,7 +84,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.513 2017/06/26 04:03:34 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.514 2017/06/26 04:09:02 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
@@ -3206,7 +3206,9 @@
 static void
 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
 {
-       uint32_t ral_lo, ral_hi;
+       uint32_t ral_lo, ral_hi, addrl, addrh;
+       uint32_t wlock_mac;
+       int rv;
 
        if (enaddr != NULL) {
                ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
@@ -3218,14 +3220,54 @@
                ral_hi = 0;
        }
 
-       if (sc->sc_type >= WM_T_82544) {
-               CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
-                   ral_lo);
-               CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
-                   ral_hi);
-       } else {
-               CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
-               CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
+       switch (sc->sc_type) {
+       case WM_T_82542_2_0:
+       case WM_T_82542_2_1:
+       case WM_T_82543:
+               CSR_WRITE(sc, WMREG_RAL(idx), ral_lo);
+               CSR_WRITE_FLUSH(sc);
+               CSR_WRITE(sc, WMREG_RAH(idx), ral_hi);
+               CSR_WRITE_FLUSH(sc);
+               break;
+       case WM_T_PCH2:
+       case WM_T_PCH_LPT:
+       case WM_T_PCH_SPT:
+               if (idx == 0) {
+                       CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
+                       CSR_WRITE_FLUSH(sc);
+                       CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
+                       CSR_WRITE_FLUSH(sc);
+                       return;
+               }
+               if (sc->sc_type != WM_T_PCH2) {
+                       wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
+                           FWSM_WLOCK_MAC);
+                       addrl = WMREG_SHRAL(idx - 1);
+                       addrh = WMREG_SHRAH(idx - 1);
+               } else {
+                       wlock_mac = 0;
+                       addrl = WMREG_PCH_LPT_SHRAL(idx - 1);
+                       addrh = WMREG_PCH_LPT_SHRAH(idx - 1);
+               }
+               
+               if ((wlock_mac == 0) || (idx <= wlock_mac)) {
+                       rv = wm_get_swflag_ich8lan(sc);
+                       if (rv != 0)
+                               return;
+                       CSR_WRITE(sc, addrl, ral_lo);
+                       CSR_WRITE_FLUSH(sc);
+                       CSR_WRITE(sc, addrh, ral_hi);
+                       CSR_WRITE_FLUSH(sc);
+                       wm_put_swflag_ich8lan(sc);
+               }
+
+               break;
+       default:
+               CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
+               CSR_WRITE_FLUSH(sc);
+               CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
+               CSR_WRITE_FLUSH(sc);
+               break;
        }
 }
 
diff -r 39aa2f9d6557 -r 72a7ac1ab791 sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Mon Jun 26 04:03:34 2017 +0000
+++ b/sys/dev/pci/if_wmreg.h    Mon Jun 26 04:09:02 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.98 2017/02/28 09:55:47 knakahara Exp $  */
+/*     $NetBSD: if_wmreg.h,v 1.99 2017/06/26 04:09:02 msaitoh Exp $    */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -636,8 +636,15 @@
 #define FEXTNVM3_PHY_CFG_COUNTER_MASK  __BITS(27, 26)
 #define FEXTNVM3_PHY_CFG_COUNTER_50MS  __BIT(27)
 
-#define        WMREG_RAL_BASE  0x0040  /* Receive Address List */
-#define        WMREG_CORDOVA_RAL_BASE 0x5400
+#define        WMREG_RAL(x)            (0x0040 + ((x) * 8)) /* Receive Address List */
+#define        WMREG_RAH(x)            (WMREG_RAL(x) + 4)
+#define        WMREG_CORDOVA_RAL(x)    (((x) <= 15) ? (0x5400 + ((x) * 8)) : \
+           (0x54e0 + (((x) - 16) * 8)))
+#define        WMREG_CORDOVA_RAH(x)    (WMREG_CORDOVA_RAL(x) + 4)
+#define        WMREG_SHRAL(x)          (0x5438 + ((x) * 8))
+#define        WMREG_SHRAH(x)          (WMREG_PCH_LPT_SHRAL(x) + 4)
+#define        WMREG_PCH_LPT_SHRAL(x)  (0x5408 + ((x) * 8))
+#define        WMREG_PCH_LPT_SHRAH(x)  (WMREG_PCH_LPT_SHRAL(x) + 4)
 #define        WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
 #define        WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
        /*
@@ -1276,7 +1283,7 @@
 #define        MNG_ICH_IAMT_MODE       0x2     /* PT mode? */
 #define        MNG_IAMT_MODE           0x3
 #define FWSM_RSPCIPHY          __BIT(6)  /* Reset PHY on PCI reset */
-#define FWSM_WLOCK_MAC         __BITS(7, 9)  /* Reset PHY on PCI reset */
+#define FWSM_WLOCK_MAC         __BITS(7, 9)
 #define FWSM_ULP_CFG_DONE      __BIT(10)
 #define FWSM_FW_VALID          __BIT(15) /* FW established a valid mode */