[src/trunk]: src/sys/dev/pci Add a workaround for BCM57780 to prevent device ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/00215726a35f
branches:  trunk
changeset: 352841:00215726a35f
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Wed Apr 12 06:22:16 2017 +0000

description:
Add a workaround for BCM57780 to prevent device timeout. This change prevent
L1PM feature do wrongy. Tested with Dell latitude 2120.

diffstat:

 sys/dev/pci/if_bge.c    |  31 +++++++++++++++++++++++++++++--
 sys/dev/pci/if_bgereg.h |  23 ++++++++++++++++++++++-
 2 files changed, 51 insertions(+), 3 deletions(-)

diffs (96 lines):

diff -r 56053d7f81bb -r 00215726a35f sys/dev/pci/if_bge.c
--- a/sys/dev/pci/if_bge.c      Wed Apr 12 06:04:34 2017 +0000
+++ b/sys/dev/pci/if_bge.c      Wed Apr 12 06:22:16 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bge.c,v 1.303 2017/04/12 06:04:34 msaitoh Exp $     */
+/*     $NetBSD: if_bge.c,v 1.304 2017/04/12 06:22:16 msaitoh Exp $     */
 
 /*
  * Copyright (c) 2001 Wind River Systems
@@ -79,7 +79,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.303 2017/04/12 06:04:34 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.304 2017/04/12 06:22:16 msaitoh Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -4257,6 +4257,13 @@
         */
        bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 
+       if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
+               val = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
+               val = (val & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
+                   | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
+               CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val);
+       }
+
        /* 5718 reset step 6, 57XX step 7 */
        reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
        /*
@@ -5510,6 +5517,26 @@
                CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg);
        }
 
+       if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) {
+               reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);
+               reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK)
+                   | BGE_PCIE_PWRMNG_L1THRESH_4MS
+                   | BGE_PCIE_PWRMNG_EXTASPMTMR_EN;
+               CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg);
+
+               reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);
+               reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK)
+                   | BGE_PCIE_EIDLE_DELAY_13CLK;
+               CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg);
+
+               /* XXX clear correctable error count */
+
+               reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
+               reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)
+                   | BGE_PCIE_LINKCTL_L1_PLL_PDDIS;
+               CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg);
+       }
+
        bge_sig_post_reset(sc, BGE_RESET_START);
 
        bge_chipinit(sc);
diff -r 56053d7f81bb -r 00215726a35f sys/dev/pci/if_bgereg.h
--- a/sys/dev/pci/if_bgereg.h   Wed Apr 12 06:04:34 2017 +0000
+++ b/sys/dev/pci/if_bgereg.h   Wed Apr 12 06:22:16 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bgereg.h,v 1.91 2015/05/17 12:06:26 msaitoh Exp $   */
+/*     $NetBSD: if_bgereg.h,v 1.92 2017/04/12 06:22:16 msaitoh Exp $   */
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -1946,6 +1946,27 @@
 #define        BGE_TLP_DATA_FIFO_PROTECT       0x02000000
 
 /*
+ * PCIe L1 config registers?
+ */
+#define        BGE_PCIE_PWRMNG_THRESH          0x7d28
+#define        BGE_PCIE_LINKCTL                0x7d54
+#define        BGE_PCIE_EIDLE_DELAY            0x7e70
+
+/* PCIe Power Management register */
+#define        BGE_PCIE_PWRMNG_L1THRESH_MASK   0x0000ff00
+#define        BGE_PCIE_PWRMNG_L1THRESH_4MS    0x0000ff00
+#define        BGE_PCIE_PWRMNG_EXTASPMTMR_EN   0x01000000
+
+/* PCIe link control register */
+#define        BGE_PCIE_LINKCTL_L1_PLL_PDEN    0x00000008
+#define        BGE_PCIE_LINKCTL_L1_PLL_PDDIS   0x00000080
+
+/* PCIe Enhanced idle delay register */
+#define        BGE_PCIE_EIDLE_DELAY_MASK       0x0000001f
+#define        BGE_PCIE_EIDLE_DELAY_13CLK      0x0000000c
+
+
+/*
  * PHY Test Control Register
  * Applicable to BCM5721 and BCM5751 only
  */