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[src/trunk]: src/sys/arch/arm/sunxi Add sun50i DE clocks.
details: https://anonhg.NetBSD.org/src/rev/80bf254f4008
branches: trunk
changeset: 447749:80bf254f4008
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Tue Jan 22 23:06:49 2019 +0000
description:
Add sun50i DE clocks.
diffstat:
sys/arch/arm/sunxi/sun4i_a10_ccu.c | 18 ++++++-----
sys/arch/arm/sunxi/sun50i_a64_ccu.c | 27 +++++++++++++++++-
sys/arch/arm/sunxi/sunxi_ccu.h | 9 ++++-
sys/arch/arm/sunxi/sunxi_ccu_fractional.c | 45 ++++++++++++++++++++++++------
4 files changed, 77 insertions(+), 22 deletions(-)
diffs (263 lines):
diff -r b666b08a8641 -r 80bf254f4008 sys/arch/arm/sunxi/sun4i_a10_ccu.c
--- a/sys/arch/arm/sunxi/sun4i_a10_ccu.c Tue Jan 22 22:22:06 2019 +0000
+++ b/sys/arch/arm/sunxi/sun4i_a10_ccu.c Tue Jan 22 23:06:49 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun4i_a10_ccu.c,v 1.9 2018/04/02 20:57:18 bouyer Exp $ */
+/* $NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.9 2018/04/02 20:57:18 bouyer Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -323,9 +323,10 @@
__BIT(15), /* div_en */
__BIT(14), /* frac_sel */
270000000, 297000000, /* frac values */
- 8, /* prediv */
- __BIT(31) /* enable */
- ),
+ 0, /* prediv */
+ 8, /* prediv_val */
+ __BIT(31), /* enable */
+ 0),
SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m",
PLL7_CFG_REG, /* reg */
__BITS(7,0), /* m */
@@ -334,9 +335,10 @@
__BIT(15), /* div_en */
__BIT(14), /* frac_sel */
270000000, 297000000, /* frac values */
- 8, /* prediv */
- __BIT(31) /* enable */
- ),
+ 0, /* prediv */
+ 8, /* prediv_val */
+ __BIT(31), /* enable */
+ 0),
SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X,
"pll_video0x2", "pll_video0",
1, 2),
diff -r b666b08a8641 -r 80bf254f4008 sys/arch/arm/sunxi/sun50i_a64_ccu.c
--- a/sys/arch/arm/sunxi/sun50i_a64_ccu.c Tue Jan 22 22:22:06 2019 +0000
+++ b/sys/arch/arm/sunxi/sun50i_a64_ccu.c Tue Jan 22 23:06:49 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun50i_a64_ccu.c,v 1.9 2018/05/18 02:03:00 jmcneill Exp $ */
+/* $NetBSD: sun50i_a64_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.9 2018/05/18 02:03:00 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -44,6 +44,7 @@
#define PLL_AUDIO_CTRL_REG 0x008
#define PLL_PERIPH0_CTRL_REG 0x028
#define PLL_PERIPH1_CTRL_REG 0x02c
+#define PLL_DE_CTRL_REG 0x048
#define AHB1_APB1_CFG_REG 0x054
#define APB2_CFG_REG 0x058
#define AHB2_CFG_REG 0x05c
@@ -59,6 +60,7 @@
#define USBPHY_CFG_REG 0x0cc
#define DRAM_CFG_REG 0x0f4
#define MBUS_RST_REG 0x0fc
+#define DE_CLK_REG 0x104
#define AC_DIG_CLK_REG 0x140
#define BUS_SOFT_RST_REG0 0x2c0
#define BUS_SOFT_RST_REG1 0x2c4
@@ -143,6 +145,7 @@
static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" };
static const char *ths_parents[] = { "hosc", NULL, NULL, NULL };
+static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = {
{ 60000000, 9, 0, 0, 2 },
@@ -259,6 +262,19 @@
SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4),
SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8),
+ SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc",
+ DE_CLK_REG, /* reg */
+ __BITS(14,8), /* m */
+ 16, /* m_min */
+ 50, /* m_max */
+ __BIT(24), /* div_en */
+ __BIT(25), /* frac_sel */
+ 270000000, 297000000, /* frac values */
+ __BITS(3,0), /* prediv */
+ 2, /* prediv_val */
+ __BIT(31), /* enable */
+ SUNXI_CCU_FRACTIONAL_PLUSONE),
+
SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents,
AHB1_APB1_CFG_REG, /* reg */
__BITS(7,6), /* prediv */
@@ -318,6 +334,13 @@
__BIT(31), /* enable */
SUNXI_CCU_DIV_TIMES_TWO),
+ SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents,
+ DE_CLK_REG, /* reg */
+ __BITS(3,0), /* div */
+ __BITS(26,24), /* sel */
+ __BIT(31), /* enable */
+ 0),
+
SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio",
AC_DIG_CLK_REG, 31),
SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x",
diff -r b666b08a8641 -r 80bf254f4008 sys/arch/arm/sunxi/sunxi_ccu.h
--- a/sys/arch/arm/sunxi/sunxi_ccu.h Tue Jan 22 22:22:06 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_ccu.h Tue Jan 22 23:06:49 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_ccu.h,v 1.19 2019/01/02 17:29:58 jmcneill Exp $ */
+/* $NetBSD: sunxi_ccu.h,v 1.20 2019/01/22 23:06:49 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -369,7 +369,10 @@
uint32_t frac_sel;
uint32_t frac[2];
uint32_t prediv;
+ uint32_t prediv_val;
uint32_t enable;
+ uint32_t flags;
+#define SUNXI_CCU_FRACTIONAL_PLUSONE __BIT(0)
};
int sunxi_ccu_fractional_enable(struct sunxi_ccu_softc *,
@@ -384,7 +387,8 @@
struct sunxi_ccu_clk *);
#define SUNXI_CCU_FRACTIONAL(_id, _name, _parent, _reg, _m, _m_min, _m_max, \
- _div_en, _frac_sel, _frac0, _frac1, _prediv, _enable) \
+ _div_en, _frac_sel, _frac0, _frac1, _prediv, _prediv_val, \
+ _enable, _flags) \
[_id] = { \
.type = SUNXI_CCU_FRACTIONAL, \
.base.name = (_name), \
@@ -394,6 +398,7 @@
.u.fractional.m_min = (_m_min), \
.u.fractional.m_max = (_m_max), \
.u.fractional.prediv = (_prediv), \
+ .u.fractional.prediv_val = (_prediv_val), \
.u.fractional.div_en = (_div_en), \
.u.fractional.frac_sel = (_frac_sel), \
.u.fractional.frac[0] = (_frac0), \
diff -r b666b08a8641 -r 80bf254f4008 sys/arch/arm/sunxi/sunxi_ccu_fractional.c
--- a/sys/arch/arm/sunxi/sunxi_ccu_fractional.c Tue Jan 22 22:22:06 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_ccu_fractional.c Tue Jan 22 23:06:49 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_ccu_fractional.c,v 1.2 2018/04/01 21:19:17 bouyer Exp $ */
+/* $NetBSD: sunxi_ccu_fractional.c,v 1.3 2019/01/22 23:06:49 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_fractional.c,v 1.2 2018/04/01 21:19:17 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_fractional.c,v 1.3 2019/01/22 23:06:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -78,10 +78,13 @@
if (rate == 0)
return 0;
- if (fractional->prediv > 0)
- rate = rate / fractional->prediv;
+ val = CCU_READ(sc, fractional->reg);
- val = CCU_READ(sc, fractional->reg);
+ if (fractional->prediv != 0) {
+ rate = rate / (__SHIFTOUT(val, fractional->prediv) + 1);
+ } else if (fractional->prediv_val > 0) {
+ rate = rate / fractional->prediv_val;
+ }
if (fractional->enable && !(val & fractional->enable))
return 0;
@@ -92,6 +95,9 @@
}
m = __SHIFTOUT(val, fractional->m);
+ if (fractional->flags & SUNXI_CCU_FRACTIONAL_PLUSONE)
+ m++;
+
return rate * m;
}
@@ -116,10 +122,19 @@
if (parent_rate == 0)
return (new_rate == 0) ? 0 : ERANGE;
- if (fractional->prediv > 0)
- parent_rate = parent_rate / fractional->prediv;
+ val = CCU_READ(sc, fractional->reg);
- val = CCU_READ(sc, fractional->reg);
+ if (fractional->prediv != 0) {
+ if (fractional->prediv_val > 0) {
+ val &= ~fractional->prediv;
+ val |= __SHIFTIN(fractional->prediv_val - 1,
+ fractional->prediv);
+ }
+ parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1);
+ } else if (fractional->prediv_val > 0) {
+ parent_rate = parent_rate / fractional->prediv_val;
+ }
+
for (i = 0; i < __arraycount(fractional->frac); i++) {
if (fractional->frac[i] == new_rate) {
val &= ~fractional->div_en;
@@ -149,6 +164,9 @@
if (best_rate == 0)
return ERANGE;
+ if (fractional->flags & SUNXI_CCU_FRACTIONAL_PLUSONE)
+ best_m--;
+
val &= ~fractional->m;
val |= __SHIFTIN(best_m, fractional->m);
CCU_WRITE(sc, fractional->reg, val);
@@ -165,6 +183,7 @@
u_int parent_rate, best_rate;
u_int m, rate;
int best_diff;
+ uint32_t val;
int i;
clkp = &clk->base;
@@ -176,8 +195,14 @@
if (parent_rate == 0)
return 0;
- if (fractional->prediv > 0)
- parent_rate = parent_rate / fractional->prediv;
+ val = CCU_READ(sc, fractional->reg);
+
+ if (fractional->prediv_val > 0) {
+ parent_rate = parent_rate / fractional->prediv_val;
+ } else if (fractional->prediv != 0) {
+ val = CCU_READ(sc, fractional->reg);
+ parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1);
+ }
for (i = 0; i < __arraycount(fractional->frac); i++) {
if (fractional->frac[i] == try_rate) {
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