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[src/trunk]: src/sys/dev/nvmm/x86 Optimize: the hardware does not clear the T...
details: https://anonhg.NetBSD.org/src/rev/50770bc063f5
branches: trunk
changeset: 448879:50770bc063f5
user: maxv <maxv%NetBSD.org@localhost>
date: Tue Feb 12 14:54:59 2019 +0000
description:
Optimize: the hardware does not clear the TLB flush command after a
VMENTRY, so clear it ourselves, to avoid uselessly flushing the guest
TLB. While here also fix the processing of EFER-induced flushes, they
shouldn't be delayed.
diffstat:
sys/dev/nvmm/x86/nvmm_x86_svm.c | 21 ++++++++++-----------
1 files changed, 10 insertions(+), 11 deletions(-)
diffs (56 lines):
diff -r ba93e52a91e4 -r 50770bc063f5 sys/dev/nvmm/x86/nvmm_x86_svm.c
--- a/sys/dev/nvmm/x86/nvmm_x86_svm.c Tue Feb 12 14:50:21 2019 +0000
+++ b/sys/dev/nvmm/x86/nvmm_x86_svm.c Tue Feb 12 14:54:59 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_svm.c,v 1.19 2019/02/04 12:11:18 maxv Exp $ */
+/* $NetBSD: nvmm_x86_svm.c,v 1.20 2019/02/12 14:54:59 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.19 2019/02/04 12:11:18 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.20 2019/02/12 14:54:59 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1194,12 +1194,6 @@
tlb_need_flush = true;
}
- if (cpudata->tlb_want_flush || tlb_need_flush) {
- vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush;
- } else {
- vmcb->ctrl.tlb_ctrl = 0;
- }
-
if (vcpu->hcpu_last != hcpu) {
vmcb->ctrl.tsc_offset = cpudata->tsc_offset +
curcpu()->ci_data.cpu_cc_skew;
@@ -1210,6 +1204,12 @@
svm_vcpu_guest_misc_enter(vcpu);
while (1) {
+ if (cpudata->tlb_want_flush || tlb_need_flush) {
+ vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush;
+ } else {
+ vmcb->ctrl.tlb_ctrl = 0;
+ }
+
s = splhigh();
svm_vcpu_guest_fpu_enter(vcpu);
svm_vmrun(cpudata->vmcb_pa, cpudata->gprs);
@@ -1219,9 +1219,8 @@
svm_vmcb_cache_default(vmcb);
if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) {
- if (cpudata->tlb_want_flush) {
- cpudata->tlb_want_flush = false;
- }
+ cpudata->tlb_want_flush = false;
+ tlb_need_flush = false;
vcpu->hcpu_last = hcpu;
}
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