[src/trunk]: src/sys/arch/arm/include Fix Normal Region Remap Register bitmas...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6c53f9e74b65
branches:  trunk
changeset: 450985:6c53f9e74b65
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu May 02 11:49:04 2019 +0000

description:
Fix Normal Region Remap Register bitmask names

diffstat:

 sys/arch/arm/include/armreg.h |  18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diffs (39 lines):

diff -r 6113deea54eb -r 6c53f9e74b65 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Thu May 02 09:19:28 2019 +0000
+++ b/sys/arch/arm/include/armreg.h     Thu May 02 11:49:04 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.125 2019/01/30 02:02:23 jmcneill Exp $    */
+/*     $NetBSD: armreg.h,v 1.126 2019/05/02 11:49:04 skrll Exp $       */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -523,12 +523,12 @@
 #define TTBCR_L_EPD0   __BIT(7)        // Don't use TTBR0
 #define TTBCR_L_T0SZ   __BITS(2,0)     // TTBR0 size offset
 
-#define NRRR_ORn(n)    __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
-#define NRRR_IRn(n)    __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
-#define NRRR_NC                0               // non-cacheable
-#define NRRR_WB_WA     1               // write-back write-allocate
-#define NRRR_WT                2               // write-through
-#define NRRR_WB                3               // write-back
+#define NMRR_ORn(n)    __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
+#define NMRR_IRn(n)    __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
+#define NMRR_NC                0               // non-cacheable
+#define NMRR_WBWA      1               // write-back write-allocate
+#define NMRR_WT                2               // write-through
+#define NMRR_WB                3               // write-back
 #define PRRR_NOSn(n)   __BITS(24+2*(n))// Memory region is Inner Shareable
 #define PRRR_NS1       __BIT(19)       // Normal Shareable S=1 is Shareable
 #define PRRR_NS0       __BIT(18)       // Normal Shareable S=0 is Shareable
@@ -870,8 +870,8 @@
 /* cp10 c10 registers */
 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
-ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
-ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
+ARMREG_READ_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
+ARMREG_WRITE_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
 /* cp15 c13 registers */
 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */