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[xsrc/trunk]: xsrc/external/mit/MesaLib/src Update generated files from a reg...
details: https://anonhg.NetBSD.org/xsrc/rev/15a05249f533
branches: trunk
changeset: 10394:15a05249f533
user: maya <maya%NetBSD.org@localhost>
date: Tue Sep 24 19:21:11 2019 +0000
description:
Update generated files from a regular build of mesa 19.1.7.
The pkgconfig files are now generated using meson, no more .pc.in files,
so I made my own using the result of the pkgsrc build.
diffstat:
external/mit/MesaLib/src/amd/common/sid_tables.h | 9304 +
external/mit/MesaLib/src/compiler/glsl/float64_glsl.h | 1746 +
external/mit/MesaLib/src/compiler/glsl/glcpp/glcpp-lex.c | 3183 +
external/mit/MesaLib/src/compiler/glsl/glcpp/glcpp-parse.c | 4638 +
external/mit/MesaLib/src/compiler/glsl/glcpp/glcpp-parse.h | 113 +
external/mit/MesaLib/src/compiler/glsl/glsl_lexer.cpp | 4675 +
external/mit/MesaLib/src/compiler/glsl/glsl_parser.cpp | 6050 +
external/mit/MesaLib/src/compiler/glsl/glsl_parser.h | 261 +
external/mit/MesaLib/src/compiler/glsl/ir_expression_operation_constant.h | 1871 +
external/mit/MesaLib/src/compiler/glsl/ir_expression_operation_strings.h | 308 +
external/mit/MesaLib/src/compiler/ir_expression_operation.h | 172 +
external/mit/MesaLib/src/compiler/nir/nir_builder_opcodes.h | 1749 +
external/mit/MesaLib/src/compiler/nir/nir_constant_expressions.c | 21021 +
external/mit/MesaLib/src/compiler/nir/nir_intrinsics.c | 3704 +
external/mit/MesaLib/src/compiler/nir/nir_intrinsics.h | 309 +
external/mit/MesaLib/src/compiler/nir/nir_opcodes.c | 4253 +
external/mit/MesaLib/src/compiler/nir/nir_opcodes.h | 301 +
external/mit/MesaLib/src/compiler/nir/nir_opt_algebraic.c | 165792 ++++++
external/mit/MesaLib/src/compiler/spirv/spirv_info.c | 915 +
external/mit/MesaLib/src/compiler/spirv/vtn_gather_types.c | 368 +
external/mit/MesaLib/src/intel/brw_nir_trig_workarounds.c | 268 +
external/mit/MesaLib/src/intel/genxml/gen10_pack.h | 11102 +
external/mit/MesaLib/src/intel/genxml/gen11_pack.h | 11248 +
external/mit/MesaLib/src/intel/genxml/gen45_pack.h | 2645 +
external/mit/MesaLib/src/intel/genxml/gen4_pack.h | 2560 +
external/mit/MesaLib/src/intel/genxml/gen5_pack.h | 2868 +
external/mit/MesaLib/src/intel/genxml/gen6_pack.h | 5319 +
external/mit/MesaLib/src/intel/genxml/gen75_pack.h | 8989 +
external/mit/MesaLib/src/intel/genxml/gen7_pack.h | 7562 +
external/mit/MesaLib/src/intel/genxml/gen8_pack.h | 9772 +
external/mit/MesaLib/src/intel/genxml/gen9_pack.h | 11410 +
external/mit/MesaLib/src/intel/genxml/genX_bits.h | 254355 ++++++++++
external/mit/MesaLib/src/intel/genxml/genX_xml.h | 24600 +
external/mit/MesaLib/src/intel/isl_format_layout.c | 5677 +
external/mit/MesaLib/src/intel/perf/gen_perf_metrics.c | 157439 ++++++
external/mit/MesaLib/src/intel/perf/gen_perf_metrics.h | 42 +
external/mit/MesaLib/src/mapi/shared-glapi_glapi_mapi_tmp.h | 5850 +-
external/mit/MesaLib/src/pkgconfig/dri.pc.in | 11 +
external/mit/MesaLib/src/pkgconfig/egl.pc.in | 11 +
external/mit/MesaLib/src/pkgconfig/gbm.pc.in | 10 +
external/mit/MesaLib/src/pkgconfig/gl.pc.in | 13 +
41 files changed, 749584 insertions(+), 2900 deletions(-)
diffs (truncated from 753734 to 300 lines):
diff -r 833d1d91f105 -r 15a05249f533 external/mit/MesaLib/src/amd/common/sid_tables.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/mit/MesaLib/src/amd/common/sid_tables.h Tue Sep 24 19:21:11 2019 +0000
@@ -0,0 +1,9304 @@
+/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */
+
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SID_TABLES_H
+#define SID_TABLES_H
+
+struct si_field {
+ unsigned name_offset;
+ unsigned mask;
+ unsigned num_values;
+ unsigned values_offset; /* offset into sid_strings_offsets */
+};
+
+struct si_reg {
+ unsigned name_offset;
+ unsigned offset;
+ unsigned num_fields;
+ unsigned fields_offset;
+};
+
+struct si_packet3 {
+ unsigned name_offset;
+ unsigned op;
+};
+
+static const struct si_packet3 packet3_table[] = {
+ {0, PKT3_NOP},
+ {4, PKT3_SET_BASE},
+ {13, PKT3_CLEAR_STATE},
+ {25, PKT3_INDEX_BUFFER_SIZE},
+ {43, PKT3_DISPATCH_DIRECT},
+ {59, PKT3_DISPATCH_INDIRECT},
+ {77, PKT3_OCCLUSION_QUERY},
+ {93, PKT3_SET_PREDICATION},
+ {109, PKT3_COND_EXEC},
+ {119, PKT3_PRED_EXEC},
+ {129, PKT3_DRAW_INDIRECT},
+ {143, PKT3_DRAW_INDEX_INDIRECT},
+ {163, PKT3_INDEX_BASE},
+ {174, PKT3_DRAW_INDEX_2},
+ {187, PKT3_CONTEXT_CONTROL},
+ {203, PKT3_INDEX_TYPE},
+ {214, PKT3_DRAW_INDIRECT_MULTI},
+ {234, PKT3_DRAW_INDEX_AUTO},
+ {250, PKT3_DRAW_INDEX_IMMD},
+ {266, PKT3_NUM_INSTANCES},
+ {280, PKT3_DRAW_INDEX_MULTI_AUTO},
+ {302, PKT3_INDIRECT_BUFFER_SI},
+ {321, PKT3_INDIRECT_BUFFER_CONST},
+ {343, PKT3_STRMOUT_BUFFER_UPDATE},
+ {365, PKT3_DRAW_INDEX_OFFSET_2},
+ {385, PKT3_WRITE_DATA},
+ {396, PKT3_DRAW_INDEX_INDIRECT_MULTI},
+ {422, PKT3_MEM_SEMAPHORE},
+ {436, PKT3_MPEG_INDEX},
+ {447, PKT3_WAIT_REG_MEM},
+ {460, PKT3_MEM_WRITE},
+ {470, PKT3_INDIRECT_BUFFER_CIK},
+ {490, PKT3_COPY_DATA},
+ {500, PKT3_PFP_SYNC_ME},
+ {512, PKT3_SURFACE_SYNC},
+ {525, PKT3_ME_INITIALIZE},
+ {539, PKT3_COND_WRITE},
+ {550, PKT3_EVENT_WRITE},
+ {562, PKT3_EVENT_WRITE_EOP},
+ {578, PKT3_RELEASE_MEM},
+ {590, PKT3_ONE_REG_WRITE},
+ {604, PKT3_ACQUIRE_MEM},
+ {616, PKT3_REWIND},
+ {623, PKT3_SET_CONFIG_REG},
+ {638, PKT3_SET_CONTEXT_REG},
+ {654, PKT3_SET_SH_REG},
+ {665, PKT3_SET_SH_REG_OFFSET},
+ {683, PKT3_SET_UCONFIG_REG},
+ {699, PKT3_SET_UCONFIG_REG_INDEX},
+ {721, PKT3_LOAD_CONST_RAM},
+ {736, PKT3_WRITE_CONST_RAM},
+ {752, PKT3_DUMP_CONST_RAM},
+ {767, PKT3_INCREMENT_CE_COUNTER},
+ {788, PKT3_INCREMENT_DE_COUNTER},
+ {809, PKT3_WAIT_ON_CE_COUNTER},
+ {828, PKT3_LOAD_CONTEXT_REG},
+ {845, PKT3_IT_OPCODE_C},
+ {857, PKT3_CP_DMA},
+ {864, PKT3_DMA_DATA},
+};
+
+static const struct si_reg sid_reg_table[] = {
+ {873, R_2C3_DRAW_INDEX_LOC, 2, 0},
+ {195, R_370_CONTROL, 4, 2},
+ {888, R_371_DST_ADDR_LO},
+ {900, R_372_DST_ADDR_HI},
+ {912, R_3F0_IB_BASE_LO},
+ {923, R_3F1_IB_BASE_HI},
+ {195, R_3F2_CONTROL, 3, 6},
+ {934, R_410_CP_DMA_WORD0, 1, 9},
+ {947, R_411_CP_DMA_WORD1, 5, 10},
+ {960, R_412_CP_DMA_WORD2, 1, 15},
+ {973, R_413_CP_DMA_WORD3, 1, 16},
+ {986, R_414_COMMAND, 11, 17},
+ {994, R_500_DMA_DATA_WORD0, 6, 28},
+ {1009, R_501_SRC_ADDR_LO},
+ {1021, R_502_SRC_ADDR_HI},
+ {888, R_503_DST_ADDR_LO},
+ {900, R_504_DST_ADDR_HI},
+ {1033, R_000E4C_SRBM_STATUS2, 21, 34},
+ {1046, R_000E50_SRBM_STATUS, 20, 55},
+ {1058, R_000E54_SRBM_STATUS3, 16, 75},
+ {1071, R_00D034_SDMA0_STATUS_REG, 29, 91},
+ {1088, R_00D834_SDMA1_STATUS_REG, 29, 91},
+ {1105, R_008008_GRBM_STATUS2, 18, 120},
+ {1118, R_008010_GRBM_STATUS, 24, 138},
+ {1130, R_00802C_GRBM_GFX_INDEX, 6, 162},
+ {1145, R_0084FC_CP_STRMOUT_CNTL, 1, 168},
+ {1161, R_0085F0_CP_COHER_CNTL, 19, 169},
+ {1175, R_0085F4_CP_COHER_SIZE},
+ {1189, R_0085F8_CP_COHER_BASE},
+ {1203, R_008014_GRBM_STATUS_SE0, 11, 188},
+ {1219, R_008018_GRBM_STATUS_SE1, 11, 199},
+ {1235, R_008038_GRBM_STATUS_SE2, 11, 210},
+ {1251, R_00803C_GRBM_STATUS_SE3, 11, 221},
+ {1145, R_0300FC_CP_STRMOUT_CNTL, 1, 232},
+ {1267, R_0301E4_CP_COHER_BASE_HI, 1, 233},
+ {1284, R_0301EC_CP_COHER_START_DELAY, 1, 234},
+ {1161, R_0301F0_CP_COHER_CNTL, 27, 235},
+ {1175, R_0301F4_CP_COHER_SIZE},
+ {1189, R_0301F8_CP_COHER_BASE},
+ {1305, R_0301FC_CP_COHER_STATUS, 4, 262},
+ {1321, R_008210_CP_CPC_STATUS, 15, 266},
+ {1335, R_008214_CP_CPC_BUSY_STAT, 28, 281},
+ {1352, R_008218_CP_CPC_STALLED_STAT1, 14, 309},
+ {1373, R_00821C_CP_CPF_STATUS, 21, 323},
+ {1387, R_008220_CP_CPF_BUSY_STAT, 31, 344},
+ {1404, R_008224_CP_CPF_STALLED_STAT1, 9, 375},
+ {1425, R_030230_CP_COHER_SIZE_HI, 1, 384},
+ {1442, R_0088B0_VGT_VTX_VECT_EJECT_REG, 1, 385},
+ {1465, R_0088C4_VGT_CACHE_INVALIDATION, 3, 386},
+ {1488, R_0088C8_VGT_ESGS_RING_SIZE},
+ {1507, R_0088CC_VGT_GSVS_RING_SIZE},
+ {1526, R_0088D4_VGT_GS_VERTEX_REUSE, 1, 389},
+ {1546, R_008958_VGT_PRIMITIVE_TYPE, 1, 390},
+ {1565, R_00895C_VGT_INDEX_TYPE, 1, 391},
+ {1580, R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0},
+ {1613, R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1},
+ {1646, R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2},
+ {1679, R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3},
+ {1712, R_008970_VGT_NUM_INDICES},
+ {1728, R_008974_VGT_NUM_INSTANCES},
+ {1746, R_008988_VGT_TF_RING_SIZE, 1, 392},
+ {1763, R_0089B0_VGT_HS_OFFCHIP_PARAM, 1, 393},
+ {1784, R_0089B8_VGT_TF_MEMORY_BASE},
+ {1803, R_008A14_PA_CL_ENHANCE, 4, 394},
+ {1817, R_008A60_PA_SU_LINE_STIPPLE_VALUE, 1, 398},
+ {1842, R_008B10_PA_SC_LINE_STIPPLE_STATE, 2, 399},
+ {1867, R_008670_CP_STALLED_STAT3, 19, 401},
+ {1884, R_008674_CP_STALLED_STAT1, 16, 420},
+ {1901, R_008678_CP_STALLED_STAT2, 29, 436},
+ {1918, R_008680_CP_STAT, 23, 465},
+ {1130, R_030800_GRBM_GFX_INDEX, 6, 488},
+ {1488, R_030900_VGT_ESGS_RING_SIZE},
+ {1507, R_030904_VGT_GSVS_RING_SIZE},
+ {1546, R_030908_VGT_PRIMITIVE_TYPE, 1, 494},
+ {1565, R_03090C_VGT_INDEX_TYPE, 1, 495},
+ {1580, R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0},
+ {1613, R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1},
+ {1646, R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2},
+ {1679, R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3},
+ {1712, R_030930_VGT_NUM_INDICES},
+ {1728, R_030934_VGT_NUM_INSTANCES},
+ {1746, R_030938_VGT_TF_RING_SIZE, 1, 496},
+ {1763, R_03093C_VGT_HS_OFFCHIP_PARAM, 2, 497},
+ {1784, R_030940_VGT_TF_MEMORY_BASE},
+ {1817, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 1, 499},
+ {1842, R_030A04_PA_SC_LINE_STIPPLE_STATE, 2, 500},
+ {1926, R_030A10_PA_SC_SCREEN_EXTENT_MIN_0, 2, 502},
+ {1952, R_030A14_PA_SC_SCREEN_EXTENT_MAX_0, 2, 504},
+ {1978, R_030A18_PA_SC_SCREEN_EXTENT_MIN_1, 2, 506},
+ {2004, R_030A2C_PA_SC_SCREEN_EXTENT_MAX_1, 2, 508},
+ {2030, R_008BF0_PA_SC_ENHANCE, 9, 510},
+ {2044, R_008C08_SQC_CACHES, 2, 519},
+ {2044, R_030D20_SQC_CACHES, 3, 521},
+ {2055, R_008C0C_SQ_RANDOM_WAVE_PRI, 3, 524},
+ {2074, R_008DFC_SQ_EXP_0, 6, 527},
+ {2083, R_030E00_TA_CS_BC_BASE_ADDR},
+ {2102, R_030E04_TA_CS_BC_BASE_ADDR_HI, 1, 533},
+ {2124, R_030F00_DB_OCCLUSION_COUNT0_LOW},
+ {2148, R_030F04_DB_OCCLUSION_COUNT0_HI, 1, 534},
+ {2171, R_008F00_SQ_BUF_RSRC_WORD0},
+ {2189, R_008F04_SQ_BUF_RSRC_WORD1, 4, 535},
+ {2207, R_030F08_DB_OCCLUSION_COUNT1_LOW},
+ {2231, R_008F08_SQ_BUF_RSRC_WORD2},
+ {2249, R_030F0C_DB_OCCLUSION_COUNT1_HI, 1, 539},
+ {2272, R_008F0C_SQ_BUF_RSRC_WORD3, 14, 540},
+ {2290, R_030F10_DB_OCCLUSION_COUNT2_LOW},
+ {2314, R_008F10_SQ_IMG_RSRC_WORD0},
+ {2332, R_030F14_DB_OCCLUSION_COUNT2_HI, 1, 554},
+ {2355, R_008F14_SQ_IMG_RSRC_WORD1, 5, 555},
+ {2373, R_030F18_DB_OCCLUSION_COUNT3_LOW},
+ {2397, R_008F18_SQ_IMG_RSRC_WORD2, 4, 560},
+ {2415, R_030F1C_DB_OCCLUSION_COUNT3_HI, 1, 564},
+ {2438, R_008F1C_SQ_IMG_RSRC_WORD3, 11, 565},
+ {2456, R_008F20_SQ_IMG_RSRC_WORD4, 2, 576},
+ {2474, R_008F24_SQ_IMG_RSRC_WORD5, 2, 578},
+ {2492, R_008F28_SQ_IMG_RSRC_WORD6, 8, 580},
+ {2510, R_008F2C_SQ_IMG_RSRC_WORD7},
+ {2528, R_008F30_SQ_IMG_SAMP_WORD0, 14, 588},
+ {2546, R_008F34_SQ_IMG_SAMP_WORD1, 4, 602},
+ {2564, R_008F38_SQ_IMG_SAMP_WORD2, 10, 606},
+ {2582, R_008F3C_SQ_IMG_SAMP_WORD3, 3, 616},
+ {2600, R_0090DC_SPI_DYN_GPR_LOCK_EN, 5, 619},
+ {2620, R_0090E0_SPI_STATIC_THREAD_MGMT_1, 2, 624},
+ {2645, R_0090E4_SPI_STATIC_THREAD_MGMT_2, 2, 626},
+ {2670, R_0090E8_SPI_STATIC_THREAD_MGMT_3, 1, 628},
+ {2695, R_0090EC_SPI_PS_MAX_WAVE_ID, 1, 629},
+ {2695, R_0090E8_SPI_PS_MAX_WAVE_ID, 1, 630},
+ {2714, R_0090F0_SPI_ARB_PRIORITY, 3, 631},
+ {2714, R_00C700_SPI_ARB_PRIORITY, 8, 634},
+ {2731, R_0090F4_SPI_ARB_CYCLES_0, 2, 642},
+ {2748, R_0090F8_SPI_ARB_CYCLES_1, 1, 644},
+ {2765, R_008F40_SQ_FLAT_SCRATCH_WORD0, 1, 645},
+ {2787, R_008F44_SQ_FLAT_SCRATCH_WORD1, 1, 646},
+ {2809, R_030FF8_DB_ZPASS_COUNT_LOW},
+ {2828, R_030FFC_DB_ZPASS_COUNT_HI, 1, 647},
+ {2846, R_031074_GDS_OA_CNTL, 1, 648},
+ {2858, R_031078_GDS_OA_COUNTER, 1, 649},
+ {2873, R_03107C_GDS_OA_ADDRESS, 5, 650},
+ {2888, R_031080_GDS_OA_INCDEC, 2, 655},
+ {2902, R_031084_GDS_OA_RING_SIZE, 1, 657},
+ {2919, R_009100_SPI_CONFIG_CNTL, 5, 658},
+ {2935, R_00913C_SPI_CONFIG_CNTL_1, 5, 663},
+ {2953, R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0, 12, 668},
+ {2083, R_00950C_TA_CS_BC_BASE_ADDR},
+ {2982, R_009858_DB_SUBTILE_CONTROL, 10, 680},
+ {3001, R_0098F8_GB_ADDR_CONFIG, 9, 690},
+ {3016, R_009910_GB_TILE_MODE0, 10, 699},
+ {3030, R_009914_GB_TILE_MODE1, 10, 699},
+ {3044, R_009918_GB_TILE_MODE2, 10, 699},
+ {3058, R_00991C_GB_TILE_MODE3, 10, 699},
+ {3072, R_009920_GB_TILE_MODE4, 10, 699},
+ {3086, R_009924_GB_TILE_MODE5, 10, 699},
+ {3100, R_009928_GB_TILE_MODE6, 10, 699},
+ {3114, R_00992C_GB_TILE_MODE7, 10, 699},
+ {3128, R_009930_GB_TILE_MODE8, 10, 699},
+ {3142, R_009934_GB_TILE_MODE9, 10, 699},
+ {3156, R_009938_GB_TILE_MODE10, 10, 699},
+ {3171, R_00993C_GB_TILE_MODE11, 10, 699},
+ {3186, R_009940_GB_TILE_MODE12, 10, 699},
+ {3201, R_009944_GB_TILE_MODE13, 10, 699},
+ {3216, R_009948_GB_TILE_MODE14, 10, 699},
+ {3231, R_00994C_GB_TILE_MODE15, 10, 699},
+ {3246, R_009950_GB_TILE_MODE16, 10, 699},
+ {3261, R_009954_GB_TILE_MODE17, 10, 699},
+ {3276, R_009958_GB_TILE_MODE18, 10, 699},
+ {3291, R_00995C_GB_TILE_MODE19, 10, 699},
+ {3306, R_009960_GB_TILE_MODE20, 10, 699},
+ {3321, R_009964_GB_TILE_MODE21, 10, 699},
+ {3336, R_009968_GB_TILE_MODE22, 10, 699},
+ {3351, R_00996C_GB_TILE_MODE23, 10, 699},
+ {3366, R_009970_GB_TILE_MODE24, 10, 699},
+ {3381, R_009974_GB_TILE_MODE25, 10, 699},
+ {3396, R_009978_GB_TILE_MODE26, 10, 699},
+ {3411, R_00997C_GB_TILE_MODE27, 10, 699},
+ {3426, R_009980_GB_TILE_MODE28, 10, 699},
+ {3441, R_009984_GB_TILE_MODE29, 10, 699},
+ {3456, R_009988_GB_TILE_MODE30, 10, 699},
+ {3471, R_00998C_GB_TILE_MODE31, 10, 699},
+ {3486, R_009990_GB_MACROTILE_MODE0, 4, 709},
+ {3505, R_009994_GB_MACROTILE_MODE1, 4, 709},
+ {3524, R_009998_GB_MACROTILE_MODE2, 4, 709},
+ {3543, R_00999C_GB_MACROTILE_MODE3, 4, 709},
+ {3562, R_0099A0_GB_MACROTILE_MODE4, 4, 709},
+ {3581, R_0099A4_GB_MACROTILE_MODE5, 4, 709},
+ {3600, R_0099A8_GB_MACROTILE_MODE6, 4, 709},
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