[src/trunk]: src/sys/dev/pci PCIe downstream ports only have a single child d...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/27918d07bb62
branches:  trunk
changeset: 460264:27918d07bb62
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Tue Oct 15 13:27:11 2019 +0000

description:
PCIe downstream ports only have a single child device, so limit probing to
dev 0.

diffstat:

 sys/dev/pci/pci.c |  24 +++++++++++++++++++-----
 1 files changed, 19 insertions(+), 5 deletions(-)

diffs (60 lines):

diff -r 354b6570e322 -r 27918d07bb62 sys/dev/pci/pci.c
--- a/sys/dev/pci/pci.c Tue Oct 15 13:21:19 2019 +0000
+++ b/sys/dev/pci/pci.c Tue Oct 15 13:27:11 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci.c,v 1.155 2019/10/14 00:20:09 jmcneill Exp $       */
+/*     $NetBSD: pci.c,v 1.156 2019/10/15 13:27:11 jmcneill Exp $       */
 
 /*
  * Copyright (c) 1995, 1996, 1997, 1998
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.155 2019/10/14 00:20:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.156 2019/10/15 13:27:11 jmcneill Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -695,17 +695,26 @@
 
        device_t bridgedev;
        bool arien = false;
+       bool downstream_port = false;
 
-       /* Check PCIe ARI */
+       /* Check PCIe ARI and port type */
        bridgedev = device_parent(sc->sc_dev);
        if (device_is_a(bridgedev, "ppb")) {
                struct ppb_softc *ppbsc = device_private(bridgedev);
                pci_chipset_tag_t ppbpc = ppbsc->sc_pc;
                pcitag_t ppbtag = ppbsc->sc_tag;
-               pcireg_t pciecap, reg;
+               pcireg_t pciecap, capreg, reg;
 
                if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS,
-                   &pciecap, NULL) != 0) {
+                   &pciecap, &capreg) != 0) {
+                       switch (PCIE_XCAP_TYPE(capreg)) {
+                       case PCIE_XCAP_TYPE_ROOT:
+                       case PCIE_XCAP_TYPE_DOWN:
+                       case PCIE_XCAP_TYPE_PCI2PCIE:
+                               downstream_port = true;
+                               break;
+                       }
+
                        reg = pci_conf_read(ppbpc, ppbtag, pciecap
                            + PCIE_DCSR2);
                        if ((reg & PCIE_DCSR2_ARI_FWD) != 0)
@@ -714,6 +723,11 @@
        }
 
        n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs));
+       if (downstream_port) {
+               /* PCIe downstream ports only have a single child device */
+               n = 1;
+       }
+
        for (i = 0; i < n; i++) {
                device = devs[i];