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[src/netbsd-9]: src/sys Pull up following revision(s) (requested by jmcneill ...
details: https://anonhg.NetBSD.org/src/rev/6c1a9f0ed4c1
branches: netbsd-9
changeset: 461127:6c1a9f0ed4c1
user: martin <martin%NetBSD.org@localhost>
date: Sat Nov 16 16:48:25 2019 +0000
description:
Pull up following revision(s) (requested by jmcneill in ticket #427):
sys/dev/ic/dw_hdmi_phy.c: revision 1.2
sys/dev/ic/dw_hdmi.c: revision 1.4
sys/dev/fdt/ausoc.c: revision 1.5
sys/dev/ic/dw_hdmi.h: revision 1.2
sys/dev/ic/dw_hdmi.h: revision 1.3
sys/dev/ic/dw_hdmi.h: revision 1.4
sys/conf/files: revision 1.1242
sys/dev/fdt/fdtvar.h: revision 1.57
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.11
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.12
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.13
sys/arch/evbarm/conf/GENERIC64: revision 1.110
sys/arch/arm/rockchip/rk_drm.c: revision 1.1
sys/arch/arm/rockchip/rk_drm.c: revision 1.2
sys/arch/evbarm/conf/GENERIC64: revision 1.112
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.1
sys/dev/fdt/fdt_clock.c: revision 1.10
sys/arch/evbarm/conf/GENERIC64: revision 1.113
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.2
sys/arch/arm/rockchip/rk_drm.h: revision 1.1
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.3
sys/arch/arm/rockchip/rk_fb.c: revision 1.1
sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.9
sys/arch/arm/rockchip/rk_vop.c: revision 1.1
sys/arch/arm/rockchip/rk_vop.c: revision 1.2
sys/arch/arm/rockchip/rk_i2c.c: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.7
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.4
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.5
sys/arch/arm/rockchip/files.rockchip: revision 1.21
sys/arch/arm/rockchip/rk_i2s.c: revision 1.1
sys/arch/arm/rockchip/files.rockchip: revision 1.22
sys/dev/ic/dw_hdmi.c: revision 1.2
sys/dev/ic/dw_hdmi_phy.c: revision 1.1
sys/dev/ic/dw_hdmi.c: revision 1.3
Support reads of more than 32 bytes in a single xfer.
Add support for internal DesignWare HDMI PHYs
Add fdtbus_clock_enable and fdtbus_clock_enable_index shortcuts
Add HDMI and VOP clocks
WIP display driver for Rockchip RK3399
Add (commented out) Rockchip display support
Select the correct MPLL and PHY settings for the requested pixel clock
Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.
Fix typo in phy config table
Fix a few swapped fields
Remove debug output
Enable Rockchip display support
Set sysclk rate at set_format time, so the link set_format callback can read the new sysclk
Add I2S audio input support.
Add software volume controls.
Add support for I2S clocks.
Add driver for Rockchip I2S/PCM controller.
Enable HDMI audio on ROCKPro64
Add rki2s
Add audio support
diffstat:
sys/arch/arm/dts/rk3399-rockpro64.dts | 6 +-
sys/arch/arm/rockchip/files.rockchip | 27 +-
sys/arch/arm/rockchip/rk3399_cru.c | 209 +++++++++-
sys/arch/arm/rockchip/rk_cru.h | 20 +-
sys/arch/arm/rockchip/rk_cru_composite.c | 66 ++-
sys/arch/arm/rockchip/rk_drm.c | 512 ++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_drm.h | 99 ++++
sys/arch/arm/rockchip/rk_dwhdmi.c | 310 ++++++++++++++
sys/arch/arm/rockchip/rk_fb.c | 160 +++++++
sys/arch/arm/rockchip/rk_i2c.c | 51 +-
sys/arch/arm/rockchip/rk_i2s.c | 638 ++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_vop.c | 659 +++++++++++++++++++++++++++++++
sys/arch/evbarm/conf/GENERIC64 | 8 +-
sys/conf/files | 3 +-
sys/dev/fdt/ausoc.c | 46 +-
sys/dev/fdt/fdt_clock.c | 28 +-
sys/dev/fdt/fdtvar.h | 4 +-
sys/dev/ic/dw_hdmi.c | 308 +++++++++++++-
sys/dev/ic/dw_hdmi.h | 39 +-
sys/dev/ic/dw_hdmi_phy.c | 401 ++++++++++++++++++
20 files changed, 3508 insertions(+), 86 deletions(-)
diffs (truncated from 4105 to 300 lines):
diff -r 79e66c410ba2 -r 6c1a9f0ed4c1 sys/arch/arm/dts/rk3399-rockpro64.dts
--- a/sys/arch/arm/dts/rk3399-rockpro64.dts Thu Nov 14 15:42:47 2019 +0000
+++ b/sys/arch/arm/dts/rk3399-rockpro64.dts Sat Nov 16 16:48:25 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399-rockpro64.dts,v 1.7 2019/07/28 10:03:56 jmcneill Exp $ */
+/* $NetBSD: rk3399-rockpro64.dts,v 1.7.2.1 2019/11/16 16:48:26 martin Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -62,6 +62,10 @@
};
};
+&hdmi_sound {
+ status = "okay";
+};
+
&pwm1 {
status = "okay";
};
diff -r 79e66c410ba2 -r 6c1a9f0ed4c1 sys/arch/arm/rockchip/files.rockchip
--- a/sys/arch/arm/rockchip/files.rockchip Thu Nov 14 15:42:47 2019 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip Sat Nov 16 16:48:25 2019 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.19 2019/05/01 10:41:33 jmcneill Exp $
+# $NetBSD: files.rockchip,v 1.19.2.1 2019/11/16 16:48:25 martin Exp $
#
# Configuration info for Rockchip family SoCs
#
@@ -78,6 +78,31 @@
attach rkpwm at fdt with rk_pwm
file arch/arm/rockchip/rk_pwm.c rk_pwm
+# DRM master
+define rkfbbus { }
+device rkdrm: drmkms, ddc_read_edid, rkfbbus
+attach rkdrm at fdt with rk_drm
+file arch/arm/rockchip/rk_drm.c rk_drm
+
+# DRM framebuffer console
+device rkfb: rkfbbus, drmfb, wsemuldisplaydev
+attach rkfb at rkfbbus with rk_fb
+file arch/arm/rockchip/rk_fb.c rk_fb
+
+# Visual Output Processor
+device rkvop: drmkms
+attach rkvop at fdt with rk_vop
+file arch/arm/rockchip/rk_vop.c rk_vop
+
+# HDMI TX (Designware based)
+attach dwhdmi at fdt with rk_dwhdmi
+file arch/arm/rockchip/rk_dwhdmi.c rk_dwhdmi
+
+# I2S/PCM controller
+device rki2s
+attach rki2s at fdt with rk_i2s
+file arch/arm/rockchip/rk_i2s.c rk_i2s
+
# SOC parameters
defflag opt_soc.h SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
diff -r 79e66c410ba2 -r 6c1a9f0ed4c1 sys/arch/arm/rockchip/rk3399_cru.c
--- a/sys/arch/arm/rockchip/rk3399_cru.c Thu Nov 14 15:42:47 2019 +0000
+++ b/sys/arch/arm/rockchip/rk3399_cru.c Sat Nov 16 16:48:25 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_cru.c,v 1.8 2019/06/09 16:14:53 jmcneill Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.8.4.1 2019/11/16 16:48:25 martin Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.8 2019/06/09 16:14:53 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.8.4.1 2019/11/16 16:48:25 martin Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -271,20 +271,21 @@
struct rk_cru_pll *pll = &clk->u.pll;
const struct rk_cru_pll_rate *pll_rate = NULL;
uint32_t val;
- int retry;
+ int retry, best_diff;
KASSERT(clk->type == RK_CRU_PLL);
if (pll->rates == NULL || rate == 0)
return EIO;
- for (int i = 0; i < pll->nrates; i++)
- if (pll->rates[i].rate == rate) {
+ best_diff = INT_MAX;
+ for (int i = 0; i < pll->nrates; i++) {
+ const int diff = (int)rate - (int)pll->rates[i].rate;
+ if (abs(diff) < best_diff) {
pll_rate = &pll->rates[i];
- break;
+ best_diff = abs(diff);
}
- if (pll_rate == NULL)
- return EINVAL;
+ }
val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);
CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
@@ -348,13 +349,23 @@
static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" };
static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" };
static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" };
+static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "npll" };
static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" };
static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" };
static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
+static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" };
+static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" };
static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" };
+static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" };
+static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" };
+static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" };
+static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" };
+static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" };
+static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
+static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" };
static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
@@ -403,7 +414,7 @@
__BIT(31), /* lock_mask */
pll_rates),
RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents,
- PLL_CON(43), /* con_base */
+ PLL_CON(48), /* con_base */
PLL_CON(51), /* mode_reg */
__BIT(8), /* mode_mask */
__BIT(31), /* lock_mask */
@@ -796,18 +807,196 @@
__BIT(1), /* gate_mask */
RK_COMPOSITE_ROUND_DOWN),
RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13),
+
+ /* VOP0 */
+ RK_COMPOSITE(RK3399_ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_parents,
+ CLKSEL_CON(47), /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(8), /* gate_mask */
+ 0),
+ RK_COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre",
+ CLKSEL_CON(47), /* div_reg */
+ __BITS(12,8), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(9), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3399_DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_parents,
+ CLKSEL_CON(49), /* muxdiv_reg */
+ __BITS(9,8), /* mux_mask */
+ __BITS(7,0), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3),
+ RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2),
+ RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)),
+
+ /* VOP1 */
+ RK_COMPOSITE(RK3399_ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_parents,
+ CLKSEL_CON(48), /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(10), /* gate_mask */
+ 0),
+ RK_COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre",
+ CLKSEL_CON(48), /* div_reg */
+ __BITS(12,8), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(11), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3399_DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_parents,
+ CLKSEL_CON(50), /* muxdiv_reg */
+ __BITS(9,8), /* mux_mask */
+ __BITS(7,0), /* div_mask */
+ CLKGATE_CON(10), /* gate_reg */
+ __BIT(13), /* gate_mask */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7),
+ RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6),
+ RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)),
+
+ /* VIO */
+ RK_COMPOSITE(RK3399_ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_parents,
+ CLKSEL_CON(42), /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(0), /* gate_mask */
+ 0),
+ RK_COMPOSITE_NOMUX(RK3399_PCLK_VIO, "pclk_vio", "aclk_vio",
+ CLKSEL_CON(43), /* div_reg */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(1), /* gate_mask */
+ 0),
+ RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12),
+
+ /* HDMI */
+ RK_COMPOSITE(RK3399_ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_parents,
+ CLKSEL_CON(42), /* muxdiv_reg */
+ __BITS(15,14), /* mux_mask */
+ __BITS(12,8), /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ 0),
+ RK_COMPOSITE_NOMUX(RK3399_PCLK_HDCP, "pclk_hdcp", "aclk_hdcp",
+ CLKSEL_CON(43), /* div_reg */
+ __BITS(14,10), /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(10), /* gate_mask */
+ 0),
+ RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents,
+ CLKSEL_CON(45), /* muxdiv_reg */
+ __BIT(15), /* mux_mask */
+ __BITS(9,0), /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(7), /* gate_mask */
+ 0),
+ RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6),
+ RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6),
+
+ /* I2S2 */
+ RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents,
+ CLKSEL_CON(28), /* muxdiv_reg */
+ __BIT(7), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(8), /* gate_reg */
+ __BIT(3), /* gate_mask */
+ 0),
+ RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents,
+ CLKSEL_CON(29), /* muxdiv_reg */
+ __BIT(7), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(8), /* gate_reg */
+ __BIT(6), /* gate_mask */
+ 0),
+ RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents,
+ CLKSEL_CON(30), /* muxdiv_reg */
+ __BIT(7), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(8), /* gate_reg */
+ __BIT(9), /* gate_mask */
+ 0),
+ RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div",
+ CLKSEL_CON(96), /* frac_reg */
+ 0),
+ RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div",
+ CLKSEL_CON(97), /* frac_reg */
+ 0),
+ RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div",
+ CLKSEL_CON(98), /* frac_reg */
+ 0),
+ RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)),
+ RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)),
+ RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)),
+ RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5),
+ RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8),
+ RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11),
+ RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0),
+ RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1),
+ RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2),
+ RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)),
+ RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents,
+ CLKSEL_CON(31), /* muxdiv_reg */
+ __BIT(2), /* mux_mask */
+ 0, /* div_mask */
+ CLKGATE_CON(8), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ RK_COMPOSITE_SET_RATE_PARENT),
+};
+
+static const struct rk3399_init_param {
+ const char *clk;
+ const char *parent;
+} rk3399_init_params[] = {
+ { .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" },
+ { .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" },
+ { .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" },
};
static void
rk3399_cru_init(struct rk_cru_softc *sc)
{
- struct rk_cru_clk *clk;
+ struct rk_cru_clk *clk, *pclk;
+ uint32_t write_mask, write_val;
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