[src/netbsd-1-4]: src/sys/arch/m68k/fpe pullup 1.4->1.5 (briggs): fix FPE

[perry <perry%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2035409a18bb
branches:  netbsd-1-4
changeset: 468800:2035409a18bb
user:      perry <perry%NetBSD.org@localhost>
date:      Mon Jun 21 15:18:50 1999 +0000

description:
pullup 1.4->1.5 (briggs): fix FPE

diffstat:

 sys/arch/m68k/fpe/fpu_emulate.h |  57 ++++++++++++----------------------------
 1 files changed, 18 insertions(+), 39 deletions(-)

diffs (109 lines):

diff -r d223ffee05a4 -r 2035409a18bb sys/arch/m68k/fpe/fpu_emulate.h
--- a/sys/arch/m68k/fpe/fpu_emulate.h   Mon Jun 21 15:18:31 1999 +0000
+++ b/sys/arch/m68k/fpe/fpu_emulate.h   Mon Jun 21 15:18:50 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_emulate.h,v 1.4 1996/04/30 11:52:14 briggs Exp $   */
+/*     $NetBSD: fpu_emulate.h,v 1.4.24.1 1999/06/21 15:18:50 perry Exp $       */
 
 /*
  * Copyright (c) 1995 Gordon Ross
@@ -44,7 +44,7 @@
  * or `unpacked' form consisting of:
  *     - sign
  *     - unbiased exponent
- *     - mantissa (`1.' + 112-bit fraction + guard + round)
+ *     - mantissa (`1.' + 63-bit fraction + guard + round)
  *     - sticky bit
  * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
  * always nonzero.  Additional low-order `guard' and `round' bits are
@@ -76,10 +76,10 @@
        int     fp_sign;                /* 0 => positive, 1 => negative */
        int     fp_exp;                 /* exponent (unbiased) */
        int     fp_sticky;              /* nonzero bits lost at right end */
-       u_int   fp_mant[4];             /* 115-bit mantissa */
+       u_int   fp_mant[3];             /* 66-bit mantissa */
 };
 
-#define        FP_NMANT        115             /* total bits in mantissa (incl g,r) */
+#define        FP_NMANT        67              /* total bits in mantissa (incl g,r) */
 #define        FP_NG           2               /* number of low-order guard bits */
 #define        FP_LG           ((FP_NMANT - 1) & 31)   /* log2(1.0) for fp_mant[0] */
 #define        FP_QUIETBIT     (1 << (FP_LG - 1))      /* Quiet bit in NaNs (0.5) */
@@ -95,7 +95,6 @@
     (dst)->fp_mant[0] = (src)->fp_mant[0];                             \
     (dst)->fp_mant[1] = (src)->fp_mant[1];                             \
     (dst)->fp_mant[2] = (src)->fp_mant[2];                             \
-    (dst)->fp_mant[3] = (src)->fp_mant[3];                             \
 }
 
 /*
@@ -170,7 +169,9 @@
 #define        EA_IMMED        0x080   /* mode (7,4): #immed */
 #define EA_MEM_INDIR   0x100   /* mode 6 or (7,3): APC@(Xn:*:*,*)@(*) etc */
 #define EA_BASE_SUPPRSS        0x200   /* mode 6 or (7,3): base register suppressed */
-    int        ea_tdisp;               /* temp. displ. used to xfer many words */
+#define EA_FRAME_EA    0x400   /* MC68LC040 only: precalculated EA from
+                                  format 4 stack frame */
+    int        ea_moffs;               /* offset used for fmoveMulti */
 };
 
 #define ea_offset      ea_ext[0]       /* mode 5: offset word */
@@ -179,13 +180,16 @@
 #define ea_basedisp    ea_ext[0]       /* mode 6: base displacement */
 #define ea_outerdisp   ea_ext[1]       /* mode 6: outer displacement */
 #define        ea_idxreg       ea_ext[2]       /* mode 6: index register number */
+#define ea_fea         ea_ext[0]       /* MC68LC040 only: frame EA */
 
 struct instruction {
-    int                is_advance;     /* length of instruction */
-    int                is_datasize;    /* byte, word, long, float, double, ... */
-    int                is_opcode;      /* opcode word */
-    int                is_word1;       /* second word */
-    struct     insn_ea is_ea0; /* decoded effective address mode */
+    u_int              is_pc;          /* insn's address */
+    u_int              is_nextpc;      /* next PC */
+    int                        is_advance;     /* length of instruction */
+    int                        is_datasize;    /* size of memory operand */
+    int                        is_opcode;      /* opcode word */
+    int                        is_word1;       /* second word */
+    struct insn_ea     is_ea;  /* decoded effective address mode */
 };
 
 /*
@@ -307,33 +311,8 @@
 /* fpu_subr.c */
 void fpu_norm __P((register struct fpn *fp));
 
-/* declarations for debugging */
-
-extern int fpu_debug_level;
-
-/* debug classes */
-#define DL_DUMPINSN 0x0001
-#define DL_DECODEEA 0x0002
-#define DL_LOADEA   0x0004
-#define DL_STOREEA  0x0008
-#define DL_OPERANDS 0x0010
-#define DL_RESULT   0x0020
-#define DL_TESTCC   0x0040
-#define DL_BRANCH   0x0080
-#define DL_FSTORE   0x0100
-#define DL_FSCALE   0x0200
-#define DL_ARITH    0x0400
-#define DL_INSN     0x0800
-#define DL_FMOVEM   0x1000
-/* not defined yet
-#define DL_2000     0x2000
-#define DL_4000     0x4000
-*/
-#define DL_VERBOSE  0x8000
-/* composit debug classes */
-#define DL_EA       (DL_DECODEEA|DL_LOADEA|DL_STOREEA)
-#define DL_VALUES   (DL_OPERANDS|DL_RESULT)
-#define DL_COND     (DL_TESTCC|DL_BRANCH)
-#define DL_ALL      0xffff
+#if !defined(FPE_DEBUG)
+#  define FPE_DEBUG 0
+#endif
 
 #endif /* _FPU_EMULATE_H_ */