Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-1-4]: src/sys/dev/pci Pull up revision 1.1 (new, requested by dro...
details: https://anonhg.NetBSD.org/src/rev/0447e4e7341b
branches: netbsd-1-4
changeset: 469529:0447e4e7341b
user: he <he%NetBSD.org@localhost>
date: Tue Oct 05 22:06:48 1999 +0000
description:
Pull up revision 1.1 (new, requested by drochner):
Back-port of driver for Alteon Gigabit Ethernet driver, originally
from FreeBSD.
diffstat:
sys/dev/pci/if_tireg.h | 1157 ++++++++++++
sys/dev/pci/ti_fw.h | 4461 ++++++++++++++++++++++++++++++++++++++++++++++++
sys/dev/pci/ti_fw2.h | 4366 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 9984 insertions(+), 0 deletions(-)
diffs (truncated from 9996 to 300 lines):
diff -r a481d26eb3f3 -r 0447e4e7341b sys/dev/pci/if_tireg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/pci/if_tireg.h Tue Oct 05 22:06:48 1999 +0000
@@ -0,0 +1,1157 @@
+/* $NetBSD: if_tireg.h,v 1.1.2.2 1999/10/05 22:06:48 he Exp $ */
+
+/*
+ * Copyright (c) 1997, 1998, 1999
+ * Bill Paul <wpaul%ctr.columbia.edu@localhost>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * FreeBSD Id: if_tireg.h,v 1.9 1999/07/27 03:54:48 wpaul Exp
+ */
+
+/*
+ * Tigon register offsets. These are memory mapped registers
+ * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
+ * Each register must be accessed using 32 bit operations.
+ *
+ * All reegisters are accessed through a 16K shared memory block.
+ * The first group of registers are actually copies of the PCI
+ * configuration space registers.
+ */
+
+/*
+ * Tigon configuration and control registers.
+ */
+#define TI_MISC_HOST_CTL 0x040
+#define TI_MISC_LOCAL_CTL 0x044
+#define TI_SEM_AB 0x048 /* Tigon 2 only */
+#define TI_MISC_CONF 0x050 /* Tigon 2 only */
+#define TI_TIMER_BITS 0x054
+#define TI_TIMERREF 0x058
+#define TI_PCI_STATE 0x05C
+#define TI_MAIN_EVENT_A 0x060
+#define TI_MAILBOX_EVENT_A 0x064
+#define TI_WINBASE 0x068
+#define TI_WINDATA 0x06C
+#define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */
+#define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */
+#define TI_TIMERREF_B 0x078 /* Tigon 2 only */
+#define TI_SERIAL 0x07C
+
+/*
+ * Misc host control bits.
+ */
+#define TI_MHC_INTSTATE 0x00000001
+#define TI_MHC_CLEARINT 0x00000002
+#define TI_MHC_RESET 0x00000008
+#define TI_MHC_BYTE_SWAP_ENB 0x00000010
+#define TI_MHC_WORD_SWAP_ENB 0x00000020
+#define TI_MHC_MASK_INTS 0x00000040
+#define TI_MHC_CHIP_REV_MASK 0xF0000000
+
+#define TI_MHC_BIGENDIAN_INIT \
+ (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
+
+#define TI_MHC_LITTLEENDIAN_INIT \
+ (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
+
+/*
+ * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
+ * Rev 5 is also the Tigon 2, but is a broken version which was never
+ * used in any actual hardware, so we ignore it.
+ */
+#define TI_REV_TIGON_I 0x40000000
+#define TI_REV_TIGON_II 0x60000000
+
+/*
+ * Firmware revision that we want.
+ */
+#define TI_FIRMWARE_MAJOR 0xc
+#define TI_FIRMWARE_MINOR 0x3
+#define TI_FIRMWARE_FIX 0xc
+
+/*
+ * Miscelaneous Local Control register.
+ */
+#define TI_MLC_EE_WRITE_ENB 0x00000010
+#define TI_MLC_SRAM_BANK_256K 0x00000200
+#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
+#define TI_MLC_LOCALADDR_21 0x00004000
+#define TI_MLC_LOCALADDR_22 0x00008000
+#define TI_MLC_SBUS_WRITEERR 0x00080000
+#define TI_MLC_EE_CLK 0x00100000
+#define TI_MLC_EE_TXEN 0x00200000
+#define TI_MLC_EE_DOUT 0x00400000
+#define TI_MLC_EE_DIN 0x00800000
+
+/*
+ * Offset of MAC address inside EEPROM.
+ */
+#define TI_EE_MAC_OFFSET 0x8c
+
+#define TI_DMA_ASSIST 0x11C
+#define TI_CPU_STATE 0x140
+#define TI_CPU_PROGRAM_COUNTER 0x144
+#define TI_SRAM_ADDR 0x154
+#define TI_SRAM_DATA 0x158
+#define TI_GEN_0 0x180
+#define TI_GEN_X 0x1FC
+#define TI_MAC_TX_STATE 0x200
+#define TI_MAC_RX_STATE 0x220
+#define TI_CPU_CTL_B 0x240 /* Tigon 2 only */
+#define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */
+#define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */
+#define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */
+#define TI_GEN_B_0 0x280 /* Tigon 2 only */
+#define TI_GEN_B_X 0x2FC /* Tigon 2 only */
+
+/*
+ * Misc config register.
+ */
+#define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */
+
+/*
+ * PCI state register.
+ */
+#define TI_PCISTATE_FORCE_RESET 0x00000001
+#define TI_PCISTATE_PROVIDE_LEN 0x00000002
+#define TI_PCISTATE_READ_MAXDMA 0x0000001C
+#define TI_PCISTATE_WRITE_MAXDMA 0x000000E0
+#define TI_PCISTATE_MINDMA 0x0000FF00
+#define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000
+#define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000
+#define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000
+#define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000
+#define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */
+#define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */
+#define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */
+#define TI_PCISTATE_READ_CMD 0x0F000000
+#define TI_PCISTATE_WRITE_CMD 0xF0000000
+
+#define TI_PCI_READMAX_4 0x04
+#define TI_PCI_READMAX_16 0x08
+#define TI_PCI_READMAX_32 0x0C
+#define TI_PCI_READMAX_64 0x10
+#define TI_PCI_READMAX_128 0x14
+#define TI_PCI_READMAX_256 0x18
+#define TI_PCI_READMAX_1024 0x1C
+
+#define TI_PCI_WRITEMAX_4 0x20
+#define TI_PCI_WRITEMAX_16 0x40
+#define TI_PCI_WRITEMAX_32 0x60
+#define TI_PCI_WRITEMAX_64 0x80
+#define TI_PCI_WRITEMAX_128 0xA0
+#define TI_PCI_WRITEMAX_256 0xC0
+#define TI_PCI_WRITEMAX_1024 0xE0
+
+#define TI_PCI_READ_CMD 0x06000000
+#define TI_PCI_WRITE_CMD 0x70000000
+
+/*
+ * DMA state register.
+ */
+#define TI_DMASTATE_ENABLE 0x00000001
+#define TI_DMASTATE_PAUSE 0x00000002
+
+/*
+ * CPU state register.
+ */
+#define TI_CPUSTATE_RESET 0x00000001
+#define TI_CPUSTATE_STEP 0x00000002
+#define TI_CPUSTATE_ROMFAIL 0x00000010
+#define TI_CPUSTATE_HALT 0x00010000
+/*
+ * MAC TX state register
+ */
+#define TI_TXSTATE_RESET 0x00000001
+#define TI_TXSTATE_ENB 0x00000002
+#define TI_TXSTATE_STOP 0x00000004
+
+/*
+ * MAC RX state register
+ */
+#define TI_RXSTATE_RESET 0x00000001
+#define TI_RXSTATE_ENB 0x00000002
+#define TI_RXSTATE_STOP 0x00000004
+
+/*
+ * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
+ * split into 64 bit registers. Only the lower 32 bits of each mailbox
+ * are used.
+ */
+#define TI_MB_HOSTINTR_HI 0x500
+#define TI_MB_HOSTINTR_LO 0x504
+#define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO
+#define TI_MB_CMDPROD_IDX_HI 0x508
+#define TI_MB_CMDPROD_IDX_LO 0x50C
+#define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO
+#define TI_MB_SENDPROD_IDX_HI 0x510
+#define TI_MB_SENDPROD_IDX_LO 0x514
+#define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO
+#define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */
+#define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */
+#define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO
+#define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */
+#define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */
+#define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO
+#define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */
+#define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */
+#define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO
+#define TI_MB_RSVD 0x530
+
+/*
+ * Tigon 2 general communication registers. These are 64 and 32 bit
+ * registers which are only valid after the firmware has been
+ * loaded and started. They actually exist in NIC memory but are
+ * mapped into the host memory via the shared memory region.
+ *
+ * The NIC internally maps these registers starting at address 0,
+ * so to determine the NIC address of any of these registers, we
+ * subtract 0x600 (the address of the first register).
+ */
+
+#define TI_GCR_BASE 0x600
+#define TI_GCR_MACADDR 0x600
+#define TI_GCR_PAR0 0x600
+#define TI_GCR_PAR1 0x604
+#define TI_GCR_GENINFO_HI 0x608
+#define TI_GCR_GENINFO_LO 0x60C
+#define TI_GCR_MCASTADDR 0x610 /* obsolete */
+#define TI_GCR_MAR0 0x610 /* obsolete */
+#define TI_GCR_MAR1 0x614 /* obsolete */
+#define TI_GCR_OPMODE 0x618
+#define TI_GCR_DMA_READCFG 0x61C
+#define TI_GCR_DMA_WRITECFG 0x620
+#define TI_GCR_TX_BUFFER_RATIO 0x624
+#define TI_GCR_EVENTCONS_IDX 0x628
+#define TI_GCR_CMDCONS_IDX 0x62C
+#define TI_GCR_TUNEPARMS 0x630
+#define TI_GCR_RX_COAL_TICKS 0x630
+#define TI_GCR_TX_COAL_TICKS 0x634
+#define TI_GCR_STAT_TICKS 0x638
+#define TI_GCR_TX_MAX_COAL_BD 0x63C
+#define TI_GCR_RX_MAX_COAL_BD 0x640
+#define TI_GCR_NIC_TRACING 0x644
+#define TI_GCR_GLINK 0x648
+#define TI_GCR_LINK 0x64C
+#define TI_GCR_NICTRACE_PTR 0x650
+#define TI_GCR_NICTRACE_START 0x654
+#define TI_GCR_NICTRACE_LEN 0x658
+#define TI_GCR_IFINDEX 0x65C
+#define TI_GCR_IFMTU 0x660
+#define TI_GCR_MASK_INTRS 0x664
+#define TI_GCR_GLINK_STAT 0x668
+#define TI_GCR_LINK_STAT 0x66C
+#define TI_GCR_RXRETURNCONS_IDX 0x680
+#define TI_GCR_CMDRING 0x700
+
+#define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE);
+
+/*
+ * Local memory window. The local memory window is a 2K shared
+ * memory region which can be used to access the NIC's internal
+ * SRAM. The window can be mapped to a given 2K region using
+ * the TI_WINDOW_BASE register.
+ */
+#define TI_WINDOW 0x800
+#define TI_WINLEN 0x800
+
+#define TI_TICKS_PER_SEC 1000000
+
+/*
+ * Operation mode register.
+ */
+#define TI_OPMODE_BYTESWAP_BD 0x00000002
+#define TI_OPMODE_WORDSWAP_BD 0x00000004
+#define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */
+#define TI_OPMODE_BYTESWAP_DATA 0x00000010
+#define TI_OPMODE_1_DMA_ACTIVE 0x00000040
+#define TI_OPMODE_SBUS 0x00000100
+#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200
+#define TI_OPMODE_INCLUDE_CRC 0x00000400
Home |
Main Index |
Thread Index |
Old Index