Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-1-4]: src/sys/dev/ic Pull up revisions 1.15-1.18 (requested by mj...
details: https://anonhg.NetBSD.org/src/rev/7bea12708366
branches: netbsd-1-4
changeset: 470013:7bea12708366
user: he <he%NetBSD.org@localhost>
date: Sat Jan 08 22:41:45 2000 +0000
description:
Pull up revisions 1.15-1.18 (requested by mjacob):
Untangle Qlogic firmware copyright problems and update firmware.
Untangle some MD support issues for said firmware. Add 1280 (Dual
LVD), 1240 (Dual Ultra), 2200 (2nd Generation Qlogic FC chipset).
Fix some synchronous negotiation problems for parallel SCSI.
Firm up some Fabric Support issues.
diffstat:
sys/dev/ic/ispreg.h | 359 +++++++++++++++++++++++++++++++++++----------------
1 files changed, 243 insertions(+), 116 deletions(-)
diffs (truncated from 468 to 300 lines):
diff -r a886cbea5740 -r 7bea12708366 sys/dev/ic/ispreg.h
--- a/sys/dev/ic/ispreg.h Sat Jan 08 22:40:58 2000 +0000
+++ b/sys/dev/ic/ispreg.h Sat Jan 08 22:41:45 2000 +0000
@@ -1,36 +1,37 @@
-/* $NetBSD: ispreg.h,v 1.14 1999/03/26 22:39:45 mjacob Exp $ */
-/* release_03_25_99 */
+/* $NetBSD: ispreg.h,v 1.14.2.1 2000/01/08 22:41:45 he Exp $ */
+/* release_6_5_99 */
/*
- * Machine Independent (well, as best as possible) register
- * definitions for Qlogic ISP SCSI adapters.
- *
- * Copyright (c) 1997, 1998, 1999 by Matthew Jacob
- * NASA/Ames Research Center
+ * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
- * notice immediately at the beginning of the file, without modification,
- * this list of conditions, and the following disclaimer.
+ * notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * derived from this software without specific prior written permission
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Machine Independent (well, as best as possible) register
+ * definitions for Qlogic ISP SCSI adapters.
+ *
+ * Matthew Jacob <mjacob%nas.nasa.gov@localhost>
+ *
*/
#ifndef _ISPREG_H
#define _ISPREG_H
@@ -54,6 +55,14 @@
* Offsets for various register blocks.
*
* Sad but true, different architectures have different offsets.
+ *
+ * Don't be alarmed if none of this makes sense. The original register
+ * layout set some defines in a certain pattern. Everything else has been
+ * grafted on since. For example, the ISP1080 manual will state that DMA
+ * registers start at 0x80 from the base of the register address space.
+ * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
+ * to start at offset 0x60 because the DMA registers are all defined to
+ * be DMA_BLOCK+0x20 and so on. Clear?
*/
#define BIU_REGS_OFF 0x00
@@ -90,47 +99,47 @@
* Bus Interface Block Register Offsets
*/
-#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */
-#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0
-#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */
-#define BIU2100_FLASH_DATA BIU_BLOCK+0x2
-#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */
-#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */
-#define BIU2100_CSR BIU_BLOCK+0x6
-#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */
-#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */
-#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */
-#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */
-#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */
+#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
+#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
+#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
+#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
+#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
+#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
+#define BIU2100_CSR (BIU_BLOCK+0x6)
+#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
+#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
+#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
+#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
+#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
#define RDMA2100_CONTROL DFIFO_COMMAND
-#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */
+#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
/*
* Putzed DMA register layouts.
*/
-#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */
+#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
#define CDMA2100_CONTROL CDMA_CONF
-#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */
-#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */
-#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */
-#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */
-#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */
-#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */
-#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */
-#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */
+#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
+#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
+#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
+#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
+#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
+#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
+#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
+#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
-#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */
+#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
#define TDMA2100_CONTROL DDMA_CONF
-#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */
-#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */
-#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */
-#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */
-#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */
-#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */
-#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */
+#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
+#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
+#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
+#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
+#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
+#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
+#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
/* these are for the 1040A cards */
-#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */
-#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */
+#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
+#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
/*
@@ -155,7 +164,8 @@
#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
-#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */
+#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
+#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
/* ISP2100 Bus Control/Status Register */
@@ -188,11 +198,11 @@
#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
-#define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \
+#define ENABLE_INTS(isp) (IS_SCSI(isp))? \
ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \
ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS)
-#define INTS_ENABLED(isp) ((isp->isp_type & ISP_HA_SCSI)? \
+#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \
(ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\
(ISP_READ(isp, BIU_ICR) & \
(BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)))
@@ -214,6 +224,8 @@
#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
+#define INT_PENDING(isp, isr) (IS_FC(isp)? \
+ ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0))
/* BUS SEMAPHORE REGISTER */
#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
@@ -309,23 +321,23 @@
* Mailbox Block Register Offsets
*/
-#define INMAILBOX0 MBOX_BLOCK+0x0
-#define INMAILBOX1 MBOX_BLOCK+0x2
-#define INMAILBOX2 MBOX_BLOCK+0x4
-#define INMAILBOX3 MBOX_BLOCK+0x6
-#define INMAILBOX4 MBOX_BLOCK+0x8
-#define INMAILBOX5 MBOX_BLOCK+0xA
-#define INMAILBOX6 MBOX_BLOCK+0xC
-#define INMAILBOX7 MBOX_BLOCK+0xE
+#define INMAILBOX0 (MBOX_BLOCK+0x0)
+#define INMAILBOX1 (MBOX_BLOCK+0x2)
+#define INMAILBOX2 (MBOX_BLOCK+0x4)
+#define INMAILBOX3 (MBOX_BLOCK+0x6)
+#define INMAILBOX4 (MBOX_BLOCK+0x8)
+#define INMAILBOX5 (MBOX_BLOCK+0xA)
+#define INMAILBOX6 (MBOX_BLOCK+0xC)
+#define INMAILBOX7 (MBOX_BLOCK+0xE)
-#define OUTMAILBOX0 MBOX_BLOCK+0x0
-#define OUTMAILBOX1 MBOX_BLOCK+0x2
-#define OUTMAILBOX2 MBOX_BLOCK+0x4
-#define OUTMAILBOX3 MBOX_BLOCK+0x6
-#define OUTMAILBOX4 MBOX_BLOCK+0x8
-#define OUTMAILBOX5 MBOX_BLOCK+0xA
-#define OUTMAILBOX6 MBOX_BLOCK+0xC
-#define OUTMAILBOX7 MBOX_BLOCK+0xE
+#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
+#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
+#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
+#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
+#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
+#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
+#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
+#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2))
#define NMBOX(isp) \
@@ -335,45 +347,48 @@
/*
* SXP Block Register Offsets
*/
-#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */
-#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */
-#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */
-#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */
-#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */
-#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */
-#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */
-#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */
-#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */
-#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */
-#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */
-#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */
-#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */
-#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */
-#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */
-#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */
-#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */
-#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */
-#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */
-#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */
-#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */
-#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */
-#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */
-#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */
-#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */
-#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */
-#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */
-#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */
-#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */
-#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */
-#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */
-#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */
-#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */
-#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */
-#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */
-#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */
-#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */
-#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */
-#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */
+#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
+#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
+#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
+#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
+#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
+#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
+#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
+#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
+#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
+#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
+#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
+#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
+#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
+#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
+#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
+#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
+#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
+#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
+#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
+#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
+#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
+#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
+#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
+#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
+#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
+#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
+#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
Home |
Main Index |
Thread Index |
Old Index