[src/netbsd-1-4]: src/sys/arch/sun3/sun3x Pull up revision 1.55 (requested by...

[he <he%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/95e72b6f3557
branches:  netbsd-1-4
changeset: 471232:95e72b6f3557
user:      he <he%NetBSD.org@localhost>
date:      Wed Jan 17 16:37:46 2001 +0000

description:
Pull up revision 1.55 (requested by tsutsui):
  Properly handle pmap->pm_refcount (initialize and lock before
  access).  Should fix long-standing "out of space in kmem_map"
  bug on sun3x.

diffstat:

 sys/arch/sun3/sun3x/pmap.c |  3911 ++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 3911 insertions(+), 0 deletions(-)

diffs (truncated from 3915 to 300 lines):

diff -r 21a6b66fbe47 -r 95e72b6f3557 sys/arch/sun3/sun3x/pmap.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/sun3/sun3x/pmap.c        Wed Jan 17 16:37:46 2001 +0000
@@ -0,0 +1,3911 @@
+/*     $NetBSD: pmap.c,v 1.45.2.2 2001/01/17 16:37:46 he Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jeremy Cooper.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * XXX These comments aren't quite accurate.  Need to change.
+ * The sun3x uses the MC68851 Memory Management Unit, which is built
+ * into the CPU.  The 68851 maps virtual to physical addresses using
+ * a multi-level table lookup, which is stored in the very memory that
+ * it maps.  The number of levels of lookup is configurable from one
+ * to four.  In this implementation, we use three, named 'A' through 'C'.
+ *
+ * The MMU translates virtual addresses into physical addresses by 
+ * traversing these tables in a proccess called a 'table walk'.  The most 
+ * significant 7 bits of the Virtual Address ('VA') being translated are 
+ * used as an index into the level A table, whose base in physical memory 
+ * is stored in a special MMU register, the 'CPU Root Pointer' or CRP.  The 
+ * address found at that index in the A table is used as the base
+ * address for the next table, the B table.  The next six bits of the VA are 
+ * used as an index into the B table, which in turn gives the base address 
+ * of the third and final C table.
+ *
+ * The next six bits of the VA are used as an index into the C table to
+ * locate a Page Table Entry (PTE).  The PTE is a physical address in memory
+ * to which the remaining 13 bits of the VA are added, producing the
+ * mapped physical address.
+ *
+ * To map the entire memory space in this manner would require 2114296 bytes 
+ * of page tables per process - quite expensive.  Instead we will 
+ * allocate a fixed but considerably smaller space for the page tables at 
+ * the time the VM system is initialized.  When the pmap code is asked by
+ * the kernel to map a VA to a PA, it allocates tables as needed from this
+ * pool.  When there are no more tables in the pool, tables are stolen
+ * from the oldest mapped entries in the tree.  This is only possible 
+ * because all memory mappings are stored in the kernel memory map
+ * structures, independent of the pmap structures.  A VA which references
+ * one of these invalidated maps will cause a page fault.  The kernel
+ * will determine that the page fault was caused by a task using a valid 
+ * VA, but for some reason (which does not concern it), that address was
+ * not mapped.  It will ask the pmap code to re-map the entry and then
+ * it will resume executing the faulting task.
+ *
+ * In this manner the most efficient use of the page table space is
+ * achieved.  Tasks which do not execute often will have their tables 
+ * stolen and reused by tasks which execute more frequently.  The best
+ * size for the page table pool will probably be determined by 
+ * experimentation.
+ *
+ * You read all of the comments so far.  Good for you.
+ * Now go play!
+ */
+
+/*** A Note About the 68851 Address Translation Cache
+ * The MC68851 has a 64 entry cache, called the Address Translation Cache
+ * or 'ATC'.  This cache stores the most recently used page descriptors
+ * accessed by the MMU when it does translations.  Using a marker called a
+ * 'task alias' the MMU can store the descriptors from 8 different table
+ * spaces concurrently.  The task alias is associated with the base
+ * address of the level A table of that address space.  When an address
+ * space is currently active (the CRP currently points to its A table)
+ * the only cached descriptors that will be obeyed are ones which have a
+ * matching task alias of the current space associated with them.
+ *
+ * Since the cache is always consulted before any table lookups are done,
+ * it is important that it accurately reflect the state of the MMU tables.
+ * Whenever a change has been made to a table that has been loaded into
+ * the MMU, the code must be sure to flush any cached entries that are
+ * affected by the change.  These instances are documented in the code at
+ * various points.
+ */
+/*** A Note About the Note About the 68851 Address Translation Cache
+ * 4 months into this code I discovered that the sun3x does not have
+ * a MC68851 chip. Instead, it has a version of this MMU that is part of the
+ * the 68030 CPU.
+ * All though it behaves very similarly to the 68851, it only has 1 task
+ * alias and a 22 entry cache.  So sadly (or happily), the first paragraph
+ * of the previous note does not apply to the sun3x pmap.
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/malloc.h>
+#include <sys/user.h>
+#include <sys/queue.h>
+#include <sys/kcore.h>
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_page.h>
+
+#include <uvm/uvm.h>
+
+#define PAGER_SVA (uvm.pager_sva)
+#define PAGER_EVA (uvm.pager_eva)
+
+#include <machine/cpu.h>
+#include <machine/kcore.h>
+#include <machine/mon.h>
+#include <machine/pmap.h>
+#include <machine/pte.h>
+#include <machine/vmparam.h>
+
+#include <sun3/sun3/cache.h>
+#include <sun3/sun3/machdep.h>
+
+#include "pmap_pvt.h"
+
+/* XXX - What headers declare these? */
+extern struct pcb *curpcb;
+extern int physmem;
+
+extern void copypage __P((const void*, void*));
+extern void zeropage __P((void*));
+
+/* Defined in locore.s */
+extern char kernel_text[];
+
+/* Defined by the linker */
+extern char etext[], edata[], end[];
+extern char *esym;     /* DDB */
+
+/*************************** DEBUGGING DEFINITIONS ***********************
+ * Macros, preprocessor defines and variables used in debugging can make *
+ * code hard to read.  Anything used exclusively for debugging purposes  *
+ * is defined here to avoid having such mess scattered around the file.  *
+ *************************************************************************/
+#ifdef PMAP_DEBUG
+/*
+ * To aid the debugging process, macros should be expanded into smaller steps
+ * that accomplish the same goal, yet provide convenient places for placing
+ * breakpoints.  When this code is compiled with PMAP_DEBUG mode defined, the
+ * 'INLINE' keyword is defined to an empty string.  This way, any function
+ * defined to be a 'static INLINE' will become 'outlined' and compiled as
+ * a separate function, which is much easier to debug.
+ */
+#define        INLINE  /* nothing */
+
+/*
+ * It is sometimes convenient to watch the activity of a particular table
+ * in the system.  The following variables are used for that purpose.
+ */
+a_tmgr_t *pmap_watch_atbl = 0;
+b_tmgr_t *pmap_watch_btbl = 0;
+c_tmgr_t *pmap_watch_ctbl = 0;
+
+int pmap_debug = 0;
+#define DPRINT(args) if (pmap_debug) printf args
+
+#else  /********** Stuff below is defined if NOT debugging **************/
+
+#define        INLINE  inline
+#define DPRINT(args)  /* nada */
+
+#endif /* PMAP_DEBUG */
+/*********************** END OF DEBUGGING DEFINITIONS ********************/
+
+/*** Management Structure - Memory Layout
+ * For every MMU table in the sun3x pmap system there must be a way to
+ * manage it; we must know which process is using it, what other tables
+ * depend on it, and whether or not it contains any locked pages.  This
+ * is solved by the creation of 'table management'  or 'tmgr'
+ * structures.  One for each MMU table in the system.
+ *
+ *                        MAP OF MEMORY USED BY THE PMAP SYSTEM
+ *
+ *      towards lower memory
+ * kernAbase -> +-------------------------------------------------------+
+ *              | Kernel     MMU A level table                          |
+ * kernBbase -> +-------------------------------------------------------+
+ *              | Kernel     MMU B level tables                         |
+ * kernCbase -> +-------------------------------------------------------+
+ *              |                                                       |
+ *              | Kernel     MMU C level tables                         |
+ *              |                                                       |
+ * mmuCbase  -> +-------------------------------------------------------+
+ *              | User       MMU C level tables                         |
+ * mmuAbase  -> +-------------------------------------------------------+
+ *              |                                                       |
+ *              | User       MMU A level tables                         |
+ *              |                                                       |
+ * mmuBbase  -> +-------------------------------------------------------+
+ *              | User       MMU B level tables                         |
+ * tmgrAbase -> +-------------------------------------------------------+
+ *              |  TMGR A level table structures                        |
+ * tmgrBbase -> +-------------------------------------------------------+
+ *              |  TMGR B level table structures                        |
+ * tmgrCbase -> +-------------------------------------------------------+
+ *              |  TMGR C level table structures                        |
+ * pvbase    -> +-------------------------------------------------------+
+ *              |  Physical to Virtual mapping table (list heads)       |
+ * pvebase   -> +-------------------------------------------------------+
+ *              |  Physical to Virtual mapping table (list elements)    |
+ *              |                                                       |
+ *              +-------------------------------------------------------+
+ *      towards higher memory
+ *
+ * For every A table in the MMU A area, there will be a corresponding
+ * a_tmgr structure in the TMGR A area.  The same will be true for
+ * the B and C tables.  This arrangement will make it easy to find the
+ * controling tmgr structure for any table in the system by use of
+ * (relatively) simple macros.
+ */
+
+/*
+ * Global variables for storing the base addresses for the areas
+ * labeled above.
+ */
+static vm_offset_t     kernAphys;
+static mmu_long_dte_t  *kernAbase;
+static mmu_short_dte_t *kernBbase;
+static mmu_short_pte_t *kernCbase;
+static mmu_short_pte_t *mmuCbase;
+static mmu_short_dte_t *mmuBbase;
+static mmu_long_dte_t  *mmuAbase;
+static a_tmgr_t                *Atmgrbase;
+static b_tmgr_t                *Btmgrbase;
+static c_tmgr_t                *Ctmgrbase;
+static pv_t            *pvbase;
+static pv_elem_t       *pvebase;
+struct pmap            kernel_pmap;
+
+/*
+ * This holds the CRP currently loaded into the MMU.
+ */
+struct mmu_rootptr kernel_crp;
+
+/*
+ * Just all around global variables.
+ */
+static TAILQ_HEAD(a_pool_head_struct, a_tmgr_struct) a_pool;
+static TAILQ_HEAD(b_pool_head_struct, b_tmgr_struct) b_pool;
+static TAILQ_HEAD(c_pool_head_struct, c_tmgr_struct) c_pool;
+
+
+/*
+ * Flags used to mark the safety/availability of certain operations or
+ * resources.
+ */
+static boolean_t pv_initialized = FALSE, /* PV system has been initialized. */
+       bootstrap_alloc_enabled = FALSE; /*Safe to use pmap_bootstrap_alloc().*/
+int tmp_vpages_inuse;  /* Temporary virtual pages are in use */
+
+/*
+ * XXX:  For now, retain the traditional variables that were
+ * used in the old pmap/vm interface (without NONCONTIG).
+ */
+/* Kernel virtual address space available: */
+vm_offset_t    virtual_avail, virtual_end;
+/* Physical address space available: */
+vm_offset_t    avail_start, avail_end;
+
+/* This keep track of the end of the contiguously mapped range. */
+vm_offset_t virtual_contig_end;
+
+/* Physical address used by pmap_next_page() */
+vm_offset_t avail_next;
+
+/* These are used by pmap_copy_page(), etc. */
+vm_offset_t tmp_vpages[2];