[src/trunk]: src/sys/arch/mips/include - MIPS processors do not impose inclus...

[nisimura <nisimura%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4c3b83c37cee
branches:  trunk
changeset: 472270:4c3b83c37cee
user:      nisimura <nisimura%NetBSD.org@localhost>
date:      Mon Apr 26 09:42:14 1999 +0000

description:
- MIPS processors do not impose inclusive (nesting) interrupt levels with
their interrupt lines.  The notion and implemention of 'spl' are left
for how target ports approach to it.

diffstat:

 sys/arch/mips/include/cpuregs.h |  15 +--------------
 1 files changed, 1 insertions(+), 14 deletions(-)

diffs (29 lines):

diff -r cf2c5819a583 -r 4c3b83c37cee sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h   Mon Apr 26 09:36:05 1999 +0000
+++ b/sys/arch/mips/include/cpuregs.h   Mon Apr 26 09:42:14 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuregs.h,v 1.20 1999/04/24 08:10:34 simonb Exp $      */
+/*     $NetBSD: cpuregs.h,v 1.21 1999/04/26 09:42:14 nisimura Exp $    */
 
 /*
  * Copyright (c) 1992, 1993
@@ -244,19 +244,6 @@
 #define MIPS_SOFT_INT_MASK_1   0x0200
 #define MIPS_SOFT_INT_MASK_0   0x0100
 
-
-/*
- * nesting interrupt masks.
- */
-#define MIPS_INT_MASK_SPL_SOFT0        MIPS_SOFT_INT_MASK_0
-#define MIPS_INT_MASK_SPL_SOFT1        (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
-#define MIPS_INT_MASK_SPL0     (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
-#define MIPS_INT_MASK_SPL1     (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
-#define MIPS_INT_MASK_SPL2     (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
-#define MIPS_INT_MASK_SPL3     (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
-#define MIPS_INT_MASK_SPL4     (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
-#define MIPS_INT_MASK_SPL5     (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
-
 /*
  * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
  */