[src/trunk]: src/sys/arch/pmax/pmax - Save Mach_splX() calls which don't fit ...

[nisimura <nisimura%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/93505327f859
branches:  trunk
changeset: 472315:93505327f859
user:      nisimura <nisimura%NetBSD.org@localhost>
date:      Tue Apr 27 08:07:26 1999 +0000

description:
- Save Mach_splX() calls which don't fit well with DECstation.  MIPS
spl machinary will be reworked, someday.

diffstat:

 sys/arch/pmax/pmax/locore_machdep.S |  15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diffs (36 lines):

diff -r 704aa9548744 -r 93505327f859 sys/arch/pmax/pmax/locore_machdep.S
--- a/sys/arch/pmax/pmax/locore_machdep.S       Tue Apr 27 06:39:49 1999 +0000
+++ b/sys/arch/pmax/pmax/locore_machdep.S       Tue Apr 27 08:07:26 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_machdep.S,v 1.9 1999/03/25 01:17:53 simonb Exp $        */
+/*     $NetBSD: locore_machdep.S,v 1.10 1999/04/27 08:07:26 nisimura Exp $     */
 
 /*
  * Copyright (c) 1992, 1993
@@ -259,6 +259,18 @@
        and     v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(splsoftnet)
 
+/* 
+ * nesting interrupt masks.
+ */
+#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
+#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
+#define MIPS_INT_MASK_SPL0      (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
+#define MIPS_INT_MASK_SPL1      (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
+#define MIPS_INT_MASK_SPL2      (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
+#define MIPS_INT_MASK_SPL3      (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
+#define MIPS_INT_MASK_SPL4      (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
+#define MIPS_INT_MASK_SPL5      (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
+
 /*
  * hardware-level spls for hardware where the device interrupt priorites
  * are ordered, and map onto mips interrupt pins in increasing priority.
@@ -422,6 +434,7 @@
  */
 LEAF(splx)
 ALEAF(_splx)
+ALEAF(_splset)
        mfc0    v0, MIPS_COP_0_STATUS_REG
        li      t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
        and     t0, t0, v0