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[src/trunk]: src/sys/arch/mips/mips - Introduce MIPS processor interrupt cont...
details: https://anonhg.NetBSD.org/src/rev/1f9d26523c2b
branches: trunk
changeset: 472784:1f9d26523c2b
user: nisimura <nisimura%NetBSD.org@localhost>
date: Fri May 07 01:30:26 1999 +0000
description:
- Introduce MIPS processor interrupt control routines;
_splraise, _spllower, _splset, _splget, _setsoftintr, _clrsoftintr, _splnone.
They manipulate MIPS processor's 8 interrupt sources and are used
as building blocks for NetBSD spl(9) kernel interface. Note that
MIPS processor doesn't enforce inclusive 'interrupt levels' found
in other processors, then the hierarchal nature of IPL must be
implemented by composing MIPS processor interrupt masks appropriately.
With the simplest target port in which small number of devices are
independently assigned with 6 external interrupt signal lines,
spl(9) kernel interface will be implemented with #define's of
processor interrupt controls mentioned above. In more general
cases, in which target computers have many devices and 'system
registers' indicating pending interrupt sources at any moment,
spl(9) will be implemented with more complex machinary manipulating
processor interrupts and system registers in target port dependent
ways.
- Nuke unused code and reorder locore definitions. XXX Following
routines will be replaced with C language version; setrunqueue,
remrunqueue, switchfpregs, savefpregs, MachFPInterrupt.
diffstat:
sys/arch/mips/mips/locore.S | 173 ++++++++++++++++++++++++++++---------------
1 files changed, 112 insertions(+), 61 deletions(-)
diffs (222 lines):
diff -r 9afa80f28efd -r 1f9d26523c2b sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S Fri May 07 00:57:46 1999 +0000
+++ b/sys/arch/mips/mips/locore.S Fri May 07 01:30:26 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.70 1999/04/24 08:10:39 simonb Exp $ */
+/* $NetBSD: locore.S,v 1.71 1999/05/07 01:30:26 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -84,16 +84,16 @@
/*
* Initialize stack and call machine startup.
*/
- la $3,start
- slt $2,$3,sp
- bne $2,$0,1f
- addu $2,$3,-CALLFRAME_SIZ
- subu $2,$3,sp
- slt $2,$2,4096 # within 4kB of _start
- beq $2,$0,2f
- addu $2,$3,-CALLFRAME_SIZ
+ la v1, start
+ slt v0, v1, sp
+ bne v0, $0, 1f
+ addu v0, v1, -CALLFRAME_SIZ
+ subu v0, v1, sp
+ slt v0, v0, 4096 # within 4KB of _start
+ beq v0, $0, 2f
+ addu v0, v1, -CALLFRAME_SIZ
1:
- move sp,$2
+ move sp, v0
2:
#ifdef __GP_SUPPORT__
la gp, _C_LABEL(_gp)
@@ -148,6 +148,7 @@
XLEAF(ultrix_esigcode)
#endif
+
/*
* The following primitives manipulate the run queues. whichqs tells which
* of the 32 queues qs have processes in them. Setrunqueue puts processes
@@ -437,35 +438,90 @@
END(longjmp)
#endif
-#if defined(NS) || defined(ISO) || defined(CCITT)
-/*
- * Insert 'p' after 'q'.
- * _insque(p, q)
- * caddr_t p, q;
- */
-LEAF(_insque)
- lw v0, 0(a1) # v0 = q->next
- sw a1, 4(a0) # p->prev = q
- sw v0, 0(a0) # p->next = q->next
- sw a0, 4(v0) # q->next->prev = p
- j ra
- sw a0, 0(a1) # q->next = p
-END(_insque)
/*
- * Remove item 'p' from queue.
- * _remque(p)
- * caddr_t p;
+ * MIPS processor interrupt control
+ *
+ * Used as building blocks for spl(9) kernel interface.
*/
-LEAF(_remque)
- lw v0, 0(a0) # v0 = p->next
- lw v1, 4(a0) # v1 = p->prev
+LEAF(_splraise)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and a0, a0, MIPS_INT_MASK # extract INT bits
+ nor a0, zero, a0 # bitwise inverse of A0
+ and a0, a0, v0 # disable retaining other bits
+ mtc0 a0, MIPS_COP_0_STATUS # store back
+ nop
+ j ra
+ and v0, v0, MIPS_INT_MASK
+END(_splraise)
+
+LEAF(_spllower)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ li v1, ~MIPS_INT_MASK
+ and v1, v0, v1 # turn off INT bit
+ nor a0, zero, a0 # bitwise inverse of A0
+ and a0, a0, MIPS_INT_MASK # extract INT bits
+ or a0, a0, v1 # disable making other bits on
+ mtc0 a0, MIPS_COP_0_STATUS # store back
+ nop
+ j ra
+ and v0, v0, MIPS_INT_MASK
+END(_spllower)
+
+LEAF(_splset)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and a0, a0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ li v1, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
+ and v1, v1, v0 # turn off every INT bit
+ or v1, v1, a0 # set old INT bits
+ mtc0 v1, MIPS_COP_0_STATUS # store back
+ nop
+ j ra
+ and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+END(_splset)
+
+LEAF(_splget)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
nop
- sw v0, 0(v1) # p->prev->next = p->next
+ j ra
+ and v0, v0, MIPS_INT_MASK
+END(_splget)
+
+LEAF(_setsoftintr)
+ mfc0 v1, MIPS_COP_0_STATUS # save status register
+ mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+ nop; nop
+ mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
+ nop
+ or v0, v0, a0 # set soft intr. bits
+ mtc0 v0, MIPS_COP_0_CAUSE # store back
+ mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
j ra
- sw v1, 4(v0) # p->next->prev = p->prev
-END(_remque)
-#endif
+ nop
+END(_setsoftintr)
+
+LEAF(_clrsoftintr)
+ mfc0 v1, MIPS_COP_0_STATUS # save status register
+ mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+ nop; nop
+ mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
+ nor a0, zero, a0 # bitwise inverse of A0
+ and v0, v0, a0 # clear soft intr. bits
+ mtc0 v0, MIPS_COP_0_CAUSE # store back
+ mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
+ j ra
+ nop
+END(_clrsoftintr)
+
+LEAF(_splnone)
+ mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
+ li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ mtc0 v0, MIPS_COP_0_STATUS # enable all sources
+ nop
+ j ra
+ nop
+END(_splnone)
+
/*
* int copystr(void *kfaddr, void *kdaddr, size_t maxlen, size_t *lencopied)
@@ -850,41 +906,36 @@
move a1, v0
#endif
-#if 0
+#if defined(NS) || defined(ISO) || defined(CCITT)
/*
- * netorder = htonl(hostorder)
- * hostorder = ntohl(netorder)
+ * Insert 'p' after 'q'.
+ * _insque(p, q)
+ * caddr_t p, q;
*/
-#if BYTE_ORDER == LITTLE_ENDIAN
-LEAF(htonl) # a0 = 0x11223344, return 0x44332211
-XLEAF(ntohl)
- srl v1, a0, 24 # v1 = 0x00000011
- sll v0, a0, 24 # v0 = 0x44000000
- or v0, v0, v1
- and v1, a0, 0xff00
- sll v1, v1, 8 # v1 = 0x00330000
- or v0, v0, v1
- srl v1, a0, 8
- and v1, v1, 0xff00 # v1 = 0x00002200
+LEAF(_insque)
+ lw v0, 0(a1) # v0 = q->next
+ sw a1, 4(a0) # p->prev = q
+ sw v0, 0(a0) # p->next = q->next
+ sw a0, 4(v0) # q->next->prev = p
j ra
- or v0, v0, v1
-END(htonl)
+ sw a0, 0(a1) # q->next = p
+END(_insque)
/*
- * netorder = htons(hostorder)
- * hostorder = ntohs(netorder)
+ * Remove item 'p' from queue.
+ * _remque(p)
+ * caddr_t p;
*/
-LEAF(htons)
-XLEAF(ntohs)
- srl v0, a0, 8
- and v0, v0, 0xff
- sll v1, a0, 8
- and v1, v1, 0xff00
+LEAF(_remque)
+ lw v0, 0(a0) # v0 = p->next
+ lw v1, 4(a0) # v1 = p->prev
+ nop
+ sw v0, 0(v1) # p->prev->next = p->next
j ra
- or v0, v0, v1
-END(htons)
+ sw v1, 4(v0) # p->next->prev = p->prev
+END(_remque)
#endif
-#endif
+
/*----------------------------------------------------------------------------
*
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