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[src/trunk]: src/sys/arch/mips/include - Redefine symbols and parameters to r...
details: https://anonhg.NetBSD.org/src/rev/6d50e1f89d5e
branches: trunk
changeset: 473137:6d50e1f89d5e
user: nisimura <nisimura%NetBSD.org@localhost>
date: Fri May 21 06:37:39 1999 +0000
description:
- Redefine symbols and parameters to represent CPU design with MIPS
nomenclature, retaining the old heritage.
- Remove API-related definitions for now obsolete utiltity routines.
diffstat:
sys/arch/mips/include/cpuregs.h | 183 +++++++++++++++++++--------------------
1 files changed, 91 insertions(+), 92 deletions(-)
diffs (truncated from 320 to 300 lines):
diff -r 928c3f300ff3 -r 6d50e1f89d5e sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Fri May 21 06:36:37 1999 +0000
+++ b/sys/arch/mips/include/cpuregs.h Fri May 21 06:37:39 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.21 1999/04/26 09:42:14 nisimura Exp $ */
+/* $NetBSD: cpuregs.h,v 1.22 1999/05/21 06:37:39 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -35,7 +35,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * @(#)machConst.h 8.1 (Berkeley) 6/10/93
+ * @(#)machConst.h 8.1 (Berkeley) 6/10/93
*
* machConst.h --
*
@@ -50,9 +50,9 @@
* without express or implied warranty.
*
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
- * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
+ * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
- * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
+ * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
*/
@@ -79,12 +79,12 @@
#define MIPS_KSEG1_START 0xa0000000
#define MIPS_KSEG2_START 0xc0000000
#define MIPS_MAX_MEM_ADDR 0xbe000000
-#define MIPS_RESERVED_ADDR 0xbfc80000
+#define MIPS_RESERVED_ADDR 0xbfc80000
-#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
-#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
-#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
-#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
+#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
+#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
+#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
+#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
#define MIPS3_VA_TO_CINDEX(x) \
@@ -346,8 +346,8 @@
/*
* R4000 MIPS-III exception vectors
*/
-#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
-#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
+#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
+#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
#define MIPS3_GEN_EXC_VEC 0x80000180
/*
@@ -368,7 +368,7 @@
*/
#define MIPS_COP_0_TLB_INDEX $0
#define MIPS_COP_0_TLB_RANDOM $1
- /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
+ /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
#define MIPS_COP_0_TLB_CONTEXT $4
/* $5 and $6 new with MIPS-III */
@@ -399,7 +399,7 @@
#define MIPS_COP_0_LLADDR $17
#define MIPS_COP_0_WATCH_LO $18
#define MIPS_COP_0_WATCH_HI $19
-#define MIPS_COP_0_TLB_XCONTEXT $20
+#define MIPS_COP_0_TLB_XCONTEXT $20
#define MIPS_COP_0_ECC $26
#define MIPS_COP_0_CACHE_ERR $27
#define MIPS_COP_0_TAG_LO $28
@@ -436,8 +436,8 @@
/*
* The floating point version and status registers.
*/
-#define MIPS_FPU_ID $0
-#define MIPS_FPU_CSR $31
+#define MIPS_FPU_ID $0
+#define MIPS_FPU_CSR $31
/*
* The floating point coprocessor status register bits.
@@ -467,7 +467,7 @@
#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
#define MIPS_FPU_COND_BIT 0x00800000
-#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
+#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
#define MIPS1_FPC_MBZ_BITS 0xff7c0000
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
@@ -483,21 +483,28 @@
/*
* The low part of the TLB entry.
*/
-#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
-#define MIPS1_TLB_PF_NUM 0xfffff000
+#define MIPS1_TLB_PFN 0xfffff000
#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
-#define MIPS1_TLB_MOD_BIT 0x00000400
+#define MIPS1_TLB_DIRTY_BIT 0x00000400
#define MIPS1_TLB_VALID_BIT 0x00000200
#define MIPS1_TLB_GLOBAL_BIT 0x00000100
-#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
-#define MIPS3_TLB_PF_NUM 0x3fffffc0
+#define MIPS3_TLB_PFN 0x3fffffc0
#define MIPS3_TLB_ATTR_MASK 0x00000038
#define MIPS3_TLB_ATTR_SHIFT 3
-#define MIPS3_TLB_MOD_BIT 0x00000004
+#define MIPS3_TLB_DIRTY_BIT 0x00000004
#define MIPS3_TLB_VALID_BIT 0x00000002
#define MIPS3_TLB_GLOBAL_BIT 0x00000001
+/* XXX XXX XXX */
+#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
+#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
+#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
+#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
+#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
+#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
+/* XXX XXX XXX */
+
/*
* MIPS3_TLB_ATTR values - coherency algorithm:
* 0: cacheable, noncoherent, write-through, no write allocate
@@ -510,7 +517,7 @@
* 7: uncached, accelerated (gather STORE operations)
*/
#define MIPS3_TLB_ATTR_WT 0 /* IDT */
-#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
+#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
@@ -522,24 +529,25 @@
/*
* The high part of the TLB entry.
*/
-#define MIPS_TLB_VIRT_PAGE_SHIFT 12
-
-#define MIPS1_TLB_VIRT_PAGE_NUM 0xfffff000
+#define MIPS1_TLB_VPN 0xfffff000
#define MIPS1_TLB_PID 0x00000fc0
#define MIPS1_TLB_PID_SHIFT 6
-#define MIPS3_TLB_VIRT_PAGE_NUM 0xffffe000
-#define MIPS3_TLB_PID 0x000000ff
-#define MIPS3_TLB_PID_SHIFT 0
+#define MIPS3_TLB_VPN2 0xffffe000
+#define MIPS3_TLB_ASID 0x000000ff
+/* XXX XXX XXX */
+#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
+#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
+#define MIPS3_TLB_PID MIPS3_TLB_ASID
+#define MIPS_TLB_VIRT_PAGE_SHIFT 12
+/* XXX XXX XXX */
/*
* r3000: shift count to put the index in the right spot.
- * (zero on r4000?)
*/
#define MIPS1_TLB_INDEX_SHIFT 8
-
/*
* The number of TLB entries and the first one that write random hits.
*/
@@ -554,92 +562,83 @@
/*
* The number of process id entries.
*/
-#define MIPS1_TLB_NUM_PIDS 64
-#define MIPS3_TLB_NUM_PIDS 256
+#define MIPS1_TLB_NUM_PIDS 64
+#define MIPS3_TLB_NUM_ASIDS 256
/*
- * backwards compatibility with existing locore and compile-time
- * mips1/mips3 binding.
+ * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
*
* XXX INT_MASK and HARD_INT_MASK are here only because we dont
* support the mips3 on-chip timer which is tied to INT_5.
*/
-#if defined(MIPS3) && !defined(MIPS1)
-#define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT
-#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS
+#if !defined(MIPS3) && defined(MIPS1)
+#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
+#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
#endif
-#if !defined(MIPS3) && defined(MIPS1)
-#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
-#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
+#if defined(MIPS3) && !defined(MIPS1)
+#define MIPS_TLB_PID_SHIFT 0
+#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
#endif
#if defined(MIPS1) && defined(MIPS3)
#define MIPS_TLB_PID_SHIFT \
- ((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT)
+ ((CPUISMIPS3)? 0 : MIPS1_TLB_PID_SHIFT)
#define MIPS_TLB_NUM_PIDS \
- ((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS)
+ ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
#endif
/*
- * TLB probe return codes.
- */
-#define MIPS_TLB_NOT_FOUND 0
-#define MIPS_TLB_FOUND 1
-#define MIPS_TLB_FOUND_WITH_PATCH 2
-#define MIPS_TLB_PROBE_ERROR 3
-
-/*
* CPU processor revision ID
*/
-#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
-#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
-#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
-#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
-#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
-#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
-#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
-#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
-#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */
-#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
-#define MIPS_R4100 0x0c /* NEC VR4100 CPU ISA III */
-#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
-#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
-#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
-#define MIPS_R4650 0x22 /* !ID crash! QED R4650 CPU ISA III */
-#define MIPS_TX3900 0x22 /* !ID crash! Toshiba R3000 CPU ISA I */
-#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
-#define MIPS_RC32364 0x26 /* IDT RC32364 CPU ISA II */
-#define MIPS_RM5230 0x28 /* QED RM5230 CPU ISA IV */
-#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 CPU ISA III */
-#define MIPS_R3SONY 0x21 /* ? Sony R3000 based CPU ISA I */
-#define MIPS_R3NKK 0x23 /* ? NKK R3000 based CPU ISA I */
-#define MIPS_R5400 0x54 /* NEC VR5400 CPU ISA IV */
+#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
+#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
+#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
+#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
+#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
+#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
+#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
+#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
+#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */
+#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
+#define MIPS_R4100 0x0c /* NEC VR4100 CPU ISA III */
+#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
+#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
+#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
+#define MIPS_R4650 0x22 /* !ID crash! QED R4650 CPU ISA III */
+#define MIPS_TX3900 0x22 /* !ID crash! Toshiba R3000 CPU ISA I */
+#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
+#define MIPS_RC32364 0x26 /* IDT RC32364 CPU ISA II */
+#define MIPS_RM5230 0x28 /* QED RM5230 CPU ISA IV */
+#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 CPU ISA III */
+#define MIPS_R3SONY 0x21 /* ? Sony R3000 based CPU ISA I */
+#define MIPS_R3NKK 0x23 /* ? NKK R3000 based CPU ISA I */
+#define MIPS_R5400 0x54 /* NEC VR5400 CPU ISA IV */
/*
* FPU processor revision ID
*/
-#define MIPS_SOFT 0x00 /* Software emulation ISA I */
-#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
-#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
-#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
-#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
-#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
-#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
-#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
-#define MIPS_R4210 0x0a /* NEC VR4210 FPC ISA III */
-#define MIPS_R4300 0x0b /* NEC VR4300 FPC ISA III */
-#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
-#define MIPS_R4600 0x20 /* QED R4600 Orion FPU ISA III */
-#define MIPS_R5010 0x23 /* MIPS R5000 FPU ISA IV */
-#define MIPS_RC32364 0x26 /* IDT RC32364 FPU ISA II */
-#define MIPS_RM5230 0x28 /* QED RM5230 FPU ISA IV */
-#define MIPS_R3SONY 0x21 /* ? Sony R3000 based FPU ISA I */
-#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */
-#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */
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