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[src/trunk]: src/sys/arch/mips - Change a symbolic name of TLB entrylo from '...
details: https://anonhg.NetBSD.org/src/rev/e041a403da53
branches: trunk
changeset: 473254:e041a403da53
user: nisimura <nisimura%NetBSD.org@localhost>
date: Thu May 27 01:56:32 1999 +0000
description:
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.
diffstat:
sys/arch/mips/include/mips1_pte.h | 14 +++++++-------
sys/arch/mips/include/mips3_pte.h | 18 +++++++++---------
sys/arch/mips/include/pte.h | 8 ++++----
sys/arch/mips/mips/db_interface.c | 8 ++++----
sys/arch/mips/mips/pmap.c | 8 ++++----
sys/arch/mips/mips/vm_machdep.c | 8 ++++----
6 files changed, 32 insertions(+), 32 deletions(-)
diffs (224 lines):
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/include/mips1_pte.h
--- a/sys/arch/mips/include/mips1_pte.h Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/include/mips1_pte.h Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips1_pte.h,v 1.10 1997/06/16 23:41:44 jonathan Exp $ */
+/* $NetBSD: mips1_pte.h,v 1.11 1999/05/27 01:56:32 nisimura Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -51,7 +51,7 @@
#if BYTE_ORDER == BIG_ENDIAN
unsigned int pg_pfnum:20, /* HW: core page frame number or 0 */
pg_n:1, /* HW: non-cacheable bit */
- pg_m:1, /* HW: modified (dirty) bit */
+ pg_m:1, /* HW: dirty bit */
pg_v:1, /* HW: valid bit */
pg_g:1, /* HW: ignore pid bit */
:4,
@@ -66,7 +66,7 @@
:4,
pg_g:1, /* HW: ignore pid bit */
pg_v:1, /* HW: valid bit */
- pg_m:1, /* HW: modified (dirty) bit */
+ pg_m:1, /* HW: dirty bit */
pg_n:1, /* HW: non-cacheable bit */
pg_pfnum:20; /* HW: core page frame number or 0 */
#endif
@@ -80,16 +80,16 @@
#define MIPS1_PG_G 0x00000100
#define MIPS1_PG_V 0x00000200
#define MIPS1_PG_NV 0x00000000
-#define MIPS1_PG_M 0x00000400
+#define MIPS1_PG_D 0x00000400
#define MIPS1_PG_N 0x00000800
#define MIPS1_PG_FRAME 0xfffff000
#define MIPS1_PG_SHIFT 12
#define MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT)
-#define MIPS1_PG_ROPAGE MIPS1_PG_V /* ??? MIPS1_PG_RO */
-#define MIPS1_PG_RWPAGE MIPS1_PG_M
+#define MIPS1_PG_ROPAGE MIPS1_PG_V
+#define MIPS1_PG_RWPAGE MIPS1_PG_D
#define MIPS1_PG_CWPAGE 0
-#define MIPS1_PG_IOPAGE (MIPS1_PG_M | MIPS1_PG_N)
+#define MIPS1_PG_IOPAGE (MIPS1_PG_D | MIPS1_PG_N)
#define mips1_pfn_to_vad(x) ((x) & MIPS1_PG_FRAME)
#define mips1_vad_to_pfn(x) (x)
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/include/mips3_pte.h
--- a/sys/arch/mips/include/mips3_pte.h Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/include/mips3_pte.h Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips3_pte.h,v 1.8 1998/09/11 16:46:31 jonathan Exp $ */
+/* $NetBSD: mips3_pte.h,v 1.9 1999/05/27 01:56:33 nisimura Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -52,15 +52,15 @@
unsigned int pg_prot:2, /* SW: access control */
pg_pfnum:24, /* HW: core page frame number or 0 */
pg_attr:3, /* HW: cache attribute */
- pg_m:1, /* HW: modified (dirty) bit */
+ pg_m:1, /* HW: dirty bit */
pg_v:1, /* HW: valid bit */
- pg_g:1; /* HW: ignore pid bit */
+ pg_g:1; /* HW: ignore asid bit */
#endif
#if BYTE_ORDER == LITTLE_ENDIAN
-unsigned int pg_g:1, /* HW: ignore pid bit */
+unsigned int pg_g:1, /* HW: ignore asid bit */
pg_v:1, /* HW: valid bit */
- pg_m:1, /* HW: modified (dirty) bit */
- pg_attr:3, /* HW: cache attribute */
+ pg_m:1, /* HW: dirty bit */
+ pg_attr:3, /* HW: cache attribute */
pg_pfnum:24, /* HW: core page frame number or 0 */
pg_prot:2; /* SW: access control */
#endif
@@ -88,7 +88,7 @@
#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
#define MIPS3_PG_V 0x00000002 /* Valid */
#define MIPS3_PG_NV 0x00000000
-#define MIPS3_PG_M 0x00000004 /* Dirty; i.e. writable */
+#define MIPS3_PG_D 0x00000004 /* Dirty */
#define MIPS3_PG_ATTR 0x0000003f
#define MIPS3_PG_UNCACHED 0x00000010
#define MIPS3_PG_CACHED 0x00000018 /* Cacheable noncoherent */
@@ -97,12 +97,12 @@
#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
/* Not wr-prot not clean */
-#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_CACHED)
+#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED)
/* Not wr-prot but clean */
#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
#define MIPS3_PG_IOPAGE \
- (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_UNCACHED)
+ (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_UNCACHED)
#define MIPS3_PG_FRAME 0x3fffffc0
#define MIPS3_PG_SHIFT 6
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/include/pte.h
--- a/sys/arch/mips/include/pte.h Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/include/pte.h Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.6 1999/01/06 04:11:25 nisimura Exp $ */
+/* $NetBSD: pte.h,v 1.7 1999/05/27 01:56:33 nisimura Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -169,8 +169,8 @@
mips_pg_m_bit()
{
if (CPUISMIPS3)
- return (MIPS3_PG_M);
- return (MIPS1_PG_M);
+ return (MIPS3_PG_D);
+ return (MIPS1_PG_D);
}
static __inline unsigned int
@@ -185,7 +185,7 @@
mips_pg_rw_bit()
{
if (CPUISMIPS3)
- return (MIPS3_PG_M);
+ return (MIPS3_PG_D);
return (MIPS1_PG_RW);
}
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/mips/db_interface.c
--- a/sys/arch/mips/mips/db_interface.c Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/mips/db_interface.c Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.16 1999/05/20 03:34:06 nisimura Exp $ */
+/* $NetBSD: db_interface.c,v 1.17 1999/05/27 01:56:34 nisimura Exp $ */
/*
* Mach Operating System
@@ -291,7 +291,7 @@
i, tlb.tlb_hi,
tlb.tlb_lo & MIPS1_PG_FRAME);
db_printf(" %c%c%c\n",
- (tlb.tlb_lo & MIPS1_PG_M) ? 'D' : ' ',
+ (tlb.tlb_lo & MIPS1_PG_D) ? 'D' : ' ',
(tlb.tlb_lo & MIPS1_PG_G) ? 'G' : ' ',
(tlb.tlb_lo & MIPS1_PG_N) ? 'N' : ' ');
}
@@ -309,12 +309,12 @@
i, tlb.tlb_hi);
db_printf("Lo0=0x%08x %c%c attr %x",
(unsigned)pfn_to_vad(tlb.tlb_lo0),
- (tlb.tlb_lo0 & MIPS3_PG_M) ? 'D' : ' ',
+ (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
(tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
(tlb.tlb_lo0 >> 3) & 7);
db_printf("Lo1=0x%08x %c%c atr %x sz=%x\n",
(unsigned)pfn_to_vad(tlb.tlb_lo1),
- (tlb.tlb_lo1 & MIPS3_PG_M) ? 'D' : ' ',
+ (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
(tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
(tlb.tlb_lo1 >> 3) & 7,
tlb.tlb_mask);
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/mips/pmap.c Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.64 1999/05/21 06:19:55 nisimura Exp $ */
+/* $NetBSD: pmap.c,v 1.65 1999/05/27 01:56:34 nisimura Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -78,7 +78,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.64 1999/05/21 06:19:55 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.65 1999/05/27 01:56:34 nisimura Exp $");
/*
* Manages physical address maps.
@@ -1181,10 +1181,10 @@
npte = (prot & VM_PROT_WRITE) ?
(MIPS3_PG_IOPAGE & ~MIPS3_PG_G) :
((MIPS3_PG_IOPAGE | MIPS3_PG_RO) &
- ~(MIPS3_PG_G | MIPS3_PG_M));
+ ~(MIPS3_PG_G | MIPS3_PG_D));
} else {
npte = (prot & VM_PROT_WRITE) ?
- (MIPS1_PG_M | MIPS1_PG_N) :
+ (MIPS1_PG_D | MIPS1_PG_N) :
(MIPS1_PG_RO | MIPS1_PG_N);
}
}
diff -r 342bdeb6d244 -r e041a403da53 sys/arch/mips/mips/vm_machdep.c
--- a/sys/arch/mips/mips/vm_machdep.c Thu May 27 01:04:13 1999 +0000
+++ b/sys/arch/mips/mips/vm_machdep.c Thu May 27 01:56:32 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vm_machdep.c,v 1.39 1999/05/26 22:19:36 thorpej Exp $ */
+/* $NetBSD: vm_machdep.c,v 1.40 1999/05/27 01:56:34 nisimura Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.39 1999/05/26 22:19:36 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.40 1999/05/27 01:56:34 nisimura Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -327,8 +327,8 @@
*/
fpte = pmap_pte(vm_map_pmap(&bp->b_proc->p_vmspace->vm_map), faddr);
tpte = pmap_pte(vm_map_pmap(phys_map), taddr);
- pt_mask = (CPUISMIPS3) ? (MIPS3_PG_V|MIPS3_PG_G|MIPS3_PG_M) :
- (MIPS1_PG_V|MIPS1_PG_G|MIPS1_PG_M);
+ pt_mask = (CPUISMIPS3) ? (MIPS3_PG_V|MIPS3_PG_G|MIPS3_PG_D) :
+ (MIPS1_PG_V|MIPS1_PG_G|MIPS1_PG_D);
do {
/* XXX should mark them PG_WIRED? */
tpte->pt_entry = fpte->pt_entry | pt_mask;
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