Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/mips/mips - Make a modification to reduce the cost ...
details: https://anonhg.NetBSD.org/src/rev/7e7b64f76422
branches: trunk
changeset: 473323:7e7b64f76422
user: nisimura <nisimura%NetBSD.org@localhost>
date: Sat May 29 09:38:28 1999 +0000
description:
- Make a modification to reduce the cost of TLBmod exception handling.
TLBUpdate() routine is used for dual purposes. In TLBmod case, just ok
to call 'tlbwi' (as designed). Result in saving of extraneous execution
path. MIPS1 only this moment.
diffstat:
sys/arch/mips/mips/locore_mips1.S | 37 ++++++++++++++++++++++++++++---------
sys/arch/mips/mips/trap.c | 12 ++++++++++--
2 files changed, 38 insertions(+), 11 deletions(-)
diffs (136 lines):
diff -r 1c7b562714eb -r 7e7b64f76422 sys/arch/mips/mips/locore_mips1.S
--- a/sys/arch/mips/mips/locore_mips1.S Sat May 29 09:31:02 1999 +0000
+++ b/sys/arch/mips/mips/locore_mips1.S Sat May 29 09:38:28 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.12 1999/05/22 02:35:35 nisimura Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.13 1999/05/29 09:38:28 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -1068,7 +1068,7 @@
* unsigned highreg, lowreg;
*
* Results:
- * None.
+ * None. (XXX not correct XXX)
*
* Side effects:
* None.
@@ -1078,6 +1078,17 @@
LEAF(mips1_TLBUpdate)
mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
+
+ li v0, -1 #
+ bne v0, a0, 3f #
+ mtc0 a1, MIPS_COP_0_TLB_LOW # this is the way MIPS
+ nop # TLB exception
+ tlbwi # handlers should be
+ nop # implemented.
+ j ra #
+ mtc0 v1, MIPS_COP_0_STATUS #
+
+3:
mfc0 t0, MIPS_COP_0_TLB_HI # Save current PID
nop # 2 cycles before intr disabled
mtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
@@ -1702,6 +1713,7 @@
mtc0 v1, MIPS_COP_0_STATUS # restore status register
END(mips1_purge_perprocess_tlb)
+#if notyet_for_PMAP_NEW
/*
* mips1_purge_single_tlb(vaddr_t)
*
@@ -1737,14 +1749,20 @@
/*
* void mips1_update_tlb(vaddr, unsigned)
*
- * Replace an entry which has the same VPN with the same TLBPID or
- * global bit, if any. If no such entry exists, add the new entry
- * into TLB victimizing a ramdomly choosen one.
+ * Used dual purposes; update current TLB entry just made TLB exception
+ * with the given entrylo value. Or, replace an entry which has the
+ * given VPN with the given TLBPID or with global bit, if any. If no
+ * such entry exists, add the new entry into TLB victimizing a ramdomly
+ * choosen one.
*/
LEAF(mips1_update_tlb)
mfc0 v1, MIPS_COP_0_STATUS # save status register
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
+ li v0, -1 # check to use current entryhi
+ beq v0, a0, 2f
+ mtc0 a1, MIPS_COP_0_TLB_LOW # set new entrylo
+
mfc0 v0, MIPS_COP_0_TLB_HI # pick current TLBPID
srl a0, 12
sll a0, 12 # obtain VPN
@@ -1754,17 +1772,18 @@
nop
tlbp # probe looking for the entry
mfc0 t0, MIPS_COP_0_TLB_INDEX # see what we got
+ nop
+ bgtz t0, 1f # index < 0 => !found
mtc0 a1, MIPS_COP_0_TLB_LOW
- bltz t0, 1f # index < 0 => !found
- nop
b 2f
- tlbwi # update an entry found
+ tlbwr # add vicitimizing another
1:
- tlbwr # add vicitimizing another
+ tlbwi # update the entry
2:
j ra
mtc0 v1, MIPS_COP_0_STATUS # restore status register
END(mips1_update_tlb)
+#endif
/*
* void mips1_clean_tlb(void)
diff -r 1c7b562714eb -r 7e7b64f76422 sys/arch/mips/mips/trap.c
--- a/sys/arch/mips/mips/trap.c Sat May 29 09:31:02 1999 +0000
+++ b/sys/arch/mips/mips/trap.c Sat May 29 09:38:28 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.109 1999/05/18 03:13:37 nisimura Exp $ */
+/* $NetBSD: trap.c,v 1.110 1999/05/29 09:38:28 nisimura Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.109 1999/05/18 03:13:37 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.110 1999/05/29 09:38:28 nisimura Exp $");
#include "opt_cputype.h" /* which mips CPU levels do we support? */
#include "opt_inet.h"
@@ -451,8 +451,12 @@
}
entry |= mips_pg_m_bit();
pte->pt_entry = entry;
+#if defined(MIPS1) && !defined(MIPS3)
+ MachTLBUpdate(~0, entry); /* use entryhi */
+#else
vaddr &= ~PGOFSET;
MachTLBUpdate(vaddr, entry);
+#endif
pa = pfn_to_vad(entry);
if (!IS_VM_PHYSADDR(pa)) {
printf("ktlbmod: va %x pa %lx\n", vaddr, pa);
@@ -484,9 +488,13 @@
}
entry |= mips_pg_m_bit();
pte->pt_entry = entry;
+#if defined(MIPS1) && !defined(MIPS3)
+ MachTLBUpdate(~0, entry); /* use entryhi */
+#else
vaddr = (vaddr & ~PGOFSET) |
(pmap->pm_asid << MIPS_TLB_PID_SHIFT);
MachTLBUpdate(vaddr, entry);
+#endif
pa = pfn_to_vad(entry);
if (!IS_VM_PHYSADDR(pa)) {
printf("utlbmod: va %x pa %lx\n", vaddr, pa);
Home |
Main Index |
Thread Index |
Old Index