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[src/trunk]: src/sys/arch/sparc64 Start reorganizing the kernel for MULTIPROC...
details: https://anonhg.NetBSD.org/src/rev/7e8368d8313e
branches: trunk
changeset: 487792:7e8368d8313e
user: eeh <eeh%NetBSD.org@localhost>
date: Mon Jun 12 23:32:46 2000 +0000
description:
Start reorganizing the kernel for MULTIPROCESSOR support.
diffstat:
sys/arch/sparc64/include/cpu.h | 31 +++++-
sys/arch/sparc64/include/param.h | 16 ++-
sys/arch/sparc64/sparc64/cpu.c | 98 +++++++++++++++--
sys/arch/sparc64/sparc64/intreg.h | 68 +------------
sys/arch/sparc64/sparc64/locore.s | 184 +++++++++++++++++++++++++---------
sys/arch/sparc64/sparc64/machdep.c | 4 +-
sys/arch/sparc64/sparc64/pmap.c | 199 ++++++++++++++++++++++++++++++------
sys/arch/sparc64/sparc64/vaddrs.h | 62 +----------
8 files changed, 435 insertions(+), 227 deletions(-)
diffs (truncated from 1204 to 300 lines):
diff -r 83c353a4529b -r 7e8368d8313e sys/arch/sparc64/include/cpu.h
--- a/sys/arch/sparc64/include/cpu.h Mon Jun 12 23:26:38 2000 +0000
+++ b/sys/arch/sparc64/include/cpu.h Mon Jun 12 23:32:46 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.18 2000/06/12 05:29:43 mrg Exp $ */
+/* $NetBSD: cpu.h,v 1.19 2000/06/12 23:32:46 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -74,14 +74,35 @@
#include <sparc64/sparc64/intreg.h>
#include <sys/sched.h>
+/*
+ * The cpu_info structure is part of a 64KB structure mapped both the kernel
+ * pmap and a single locked TTE a CPUINFO_VA for that particular processor.
+ * Each processor's cpu_info is accessible at CPUINFO_VA only for that
+ * processor. Other processors can access that through an additional mapping
+ * in the kernel pmap.
+ *
+ * The 64KB page contains:
+ *
+ * cpu_info
+ * interrupt stack (all remaining space)
+ * idle PCB
+ * idle stack (STACKSPACE - sizeof(PCB))
+ * 32KB TSB
+ */
+
struct cpu_info {
+ struct proc *ci_curproc;
+ struct pcb *ci_cpcb;
+ struct cpu_info *ci_next;
+ int ci_number;
struct schedstate_percpu ci_schedstate; /* scheduler state */
#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
- u_long ci_spin_locks; /* # of spin locks held */
- u_long ci_simple_locks; /* # of simple locks held */
+ u_long ci_spin_locks; /* # of spin locks held */
+ u_long ci_simple_locks;/* # of simple locks held */
#endif
};
+extern struct cpu_info *cpus;
extern struct cpu_info cpu_info_store;
#define curcpu() (&cpu_info_store)
@@ -93,7 +114,7 @@
#define cpu_swapin(p) /* nothing */
#define cpu_swapout(p) /* nothing */
#define cpu_wait(p) /* nothing */
-#define cpu_number() 0
+#define cpu_number() (curcpu()->ci_number)
/*
* Arguments to hardclock, softclock and gatherstats encapsulate the
@@ -188,6 +209,8 @@
void intr_establish __P((int level, struct intrhand *));
+/* cpu.c */
+u_int64_t cpu_start __P((int));
/* disksubr.c */
struct dkbad;
int isbad __P((struct dkbad *bt, int, int, int));
diff -r 83c353a4529b -r 7e8368d8313e sys/arch/sparc64/include/param.h
--- a/sys/arch/sparc64/include/param.h Mon Jun 12 23:26:38 2000 +0000
+++ b/sys/arch/sparc64/include/param.h Mon Jun 12 23:32:46 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: param.h,v 1.17 2000/05/22 02:35:24 mrg Exp $ */
+/* $NetBSD: param.h,v 1.18 2000/06/12 23:32:46 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -120,8 +120,8 @@
extern int nbpg, pgofset, pgshift;
#endif
-#define KERNBASE 0xf1000000 /* start of kernel virtual space */
-#define KERNEND 0xfe000000 /* start of kernel virtual space */
+#define KERNBASE 0x0f1000000 /* start of kernel virtual space */
+#define KERNEND 0x0fe000000 /* end of kernel virtual space */
#define VM_MAX_KERNEL_BUF ((KERNEND-KERNBASE)/4)
#define DEV_BSIZE 512
@@ -131,13 +131,19 @@
#ifdef __arch64__
/* We get stack overflows w/8K stacks in 64-bit mode */
-#define SSIZE 2 /* initial stack size in pages */
+#define SSIZE 1 /* initial stack size in pages */
#else
#define SSIZE 1
#endif
#define USPACE (SSIZE*8192)
/*
+ * Here's the location of the interrupt stack and CPU structure.
+ */
+#define INTSTACK (KERNEND)
+#define EINTSTACK (INTSTACK+USPACE
+
+/*
* Constants related to network buffer management.
* MCLBYTES must be no larger than NBPG (the software page size), and,
* on machines that exchange pages of input or output buffers with mbuf
@@ -202,6 +208,7 @@
*/
#ifdef _KERNEL
#ifndef _LOCORE
+#if 0
extern vaddr_t dvma_base;
extern vaddr_t dvma_end;
extern struct map *dvmamap;
@@ -215,6 +222,7 @@
extern caddr_t kdvma_mapin __P((caddr_t, int, int));
extern caddr_t dvma_malloc __P((size_t, void *, int));
extern void dvma_free __P((caddr_t, size_t, void *));
+#endif
extern void delay __P((unsigned int));
#define DELAY(n) delay(n)
diff -r 83c353a4529b -r 7e8368d8313e sys/arch/sparc64/sparc64/cpu.c
--- a/sys/arch/sparc64/sparc64/cpu.c Mon Jun 12 23:26:38 2000 +0000
+++ b/sys/arch/sparc64/sparc64/cpu.c Mon Jun 12 23:32:46 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.5 1999/11/06 20:18:13 eeh Exp $ */
+/* $NetBSD: cpu.c,v 1.6 2000/06/12 23:32:47 eeh Exp $ */
/*
* Copyright (c) 1996
@@ -56,6 +56,7 @@
#include <sys/device.h>
#include <vm/vm.h>
+#include <vm/vm_kern.h>
#include <machine/autoconf.h>
#include <machine/cpu.h>
@@ -69,6 +70,12 @@
/* This is declared here so that you must include a CPU for the cache code. */
struct cacheinfo cacheinfo;
+/* Our exported CPU info; we have only one for now. */
+struct cpu_info cpu_info_store;
+
+/* Linked list of all CPUs in system. */
+struct cpu_info *cpus = NULL;
+
/* The following are used externally (sysctl_hw). */
char machine[] = MACHINE; /* from <machine/param.h> */
char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
@@ -118,18 +125,85 @@
#endif
/*
- * 4/110 comment: the 4/110 chops off the top 4 bits of an OBIO address.
- * this confuses autoconf. for example, if you try and map
- * 0xfe000000 in obio space on a 4/110 it actually maps 0x0e000000.
- * this is easy to verify with the PROM. this causes problems
- * with devices like "esp0 at obio0 addr 0xfa000000" because the
- * 4/110 treats it as esp0 at obio0 addr 0x0a000000" which is the
- * address of the 4/110's "sw0" scsi chip. the same thing happens
- * between zs1 and zs2. since the sun4 line is "closed" and
- * we know all the "obio" devices that will ever be on it we just
- * put in some special case "if"'s in the match routines of esp,
- * dma, and zs.
+ * Overhead involved in firing up a new CPU:
+ *
+ * Allocate a cpuinfo/interrupt stack
+ * Map that into the kernel
+ * Initialize the cpuinfo
+ * Return the TLB entry for the cpuinfo.
*/
+u_int64_t
+cpu_start(cpu_num)
+ int cpu_num;
+{
+ struct cpu_info *ci;
+ u_int64_t pagesize;
+ u_int64_t pte;
+ vm_page_t m;
+ paddr_t pa;
+ psize_t size;
+ vaddr_t va;
+ struct pglist mlist;
+ int error;
+
+ size = NBPG; /* XXXX 8K, 64K, 512K, or 4MB */
+ TAILQ_INIT(&mlist);
+ if ((error = uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1,
+ (paddr_t)size, (paddr_t)0, &mlist, 1, 0)) != 0)
+ panic("cpu_start: no memory, error %d", error);
+
+ va = uvm_km_valloc(kernel_map, size);
+ if (va == 0)
+ panic("cpu_start: no memory");
+
+ m = TAILQ_FIRST(&mlist);
+ pa = VM_PAGE_TO_PHYS(m);
+ pte = TSB_DATA(0 /* global */,
+ pagesize,
+ pa,
+ 1 /* priv */,
+ 1 /* Write */,
+ 1 /* Cacheable */,
+ 1 /* ALIAS -- Disable D$ */,
+ 1 /* valid */,
+ 0 /* IE */);
+
+ /* Map the pages */
+ for (; m != NULL; m = TAILQ_NEXT(m,pageq)) {
+ pa = VM_PAGE_TO_PHYS(m);
+ pmap_zero_page(pa);
+ pmap_enter(pmap_kernel(), va, pa | PMAP_NVC,
+ VM_PROT_READ|VM_PROT_WRITE,
+ VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED);
+ va += NBPG;
+ }
+ if (!cpus) cpus = (struct cpu_info *)va;
+ else {
+ for (ci = cpus; ci->ci_next; ci=ci->ci_next);
+ ci->ci_next = (struct cpu_info *)va;
+ }
+
+ switch (size) {
+#define K *1024
+ case 8 K:
+ pagesize = TLB_8K;
+ break;
+ case 64 K:
+ pagesize = TLB_64K;
+ break;
+ case 512 K:
+ pagesize = TLB_512K;
+ break;
+ case 4 K K:
+ pagesize = TLB_4M;
+ break;
+ default:
+ panic("cpu_start: stack size %x not a machine page size\n",
+ size);
+ }
+ return (pte|TLB_L);
+}
+
int
cpu_match(parent, cf, aux)
diff -r 83c353a4529b -r 7e8368d8313e sys/arch/sparc64/sparc64/intreg.h
--- a/sys/arch/sparc64/sparc64/intreg.h Mon Jun 12 23:26:38 2000 +0000
+++ b/sys/arch/sparc64/sparc64/intreg.h Mon Jun 12 23:32:46 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intreg.h,v 1.2 2000/03/16 02:36:59 eeh Exp $ */
+/* $NetBSD: intreg.h,v 1.3 2000/06/12 23:32:47 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -73,71 +73,5 @@
#ifndef _LOCORE
struct intrhand; /* This is in cpu.h if you need it. */
void send_softint __P((int cpu, int level, struct intrhand *ih));
-#if 0
-void ienab_bis __P((int bis)); /* set given bits */
-void ienab_bic __P((int bic)); /* clear given bits */
-#endif
-#endif
-
-#if 0
-#if defined(SUN4M)
-#ifdef notyet
-#define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc)
-#define IENAB_P0 0x0008
-#define IENAB_P1 0x1008
-#define IENAB_P2 0x2008
-#define IENAB_P3 0x3008
-#endif /* notyet */
#endif
-#if defined(SUN4M)
-/*
- * Interrupt Control Registers, located in IO space.
- * (mapped to `locore' for now..)
- * There are two sets of interrupt registers called `Processor Interrupts'
- * and `System Interrupts'. The `Processor' set corresponds to the 15
- * interrupt levels as seen by the CPU. The `System' set corresponds to
- * a set of devices supported by the implementing chip-set.
- *
- * Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are
- * system-wide interrupts, and the ICR_ITR selects the processor to get
- * the system's interrupts.
- */
-#define ICR_PI_PEND (PI_INTR_VA + 0x0)
-#define ICR_PI_CLR (PI_INTR_VA + 0x4)
-#define ICR_PI_SET (PI_INTR_VA + 0x8)
-#define ICR_SI_PEND (SI_INTR_VA)
-#define ICR_SI_MASK (SI_INTR_VA + 0x4)
-#define ICR_SI_CLR (SI_INTR_VA + 0x8)
-#define ICR_SI_SET (SI_INTR_VA + 0xc)
-#define ICR_ITR (SI_INTR_VA + 0x10)
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