[src/netbsd-1-5]: src/sys/arch/sparc64/sparc64 pull up 1.3 (approved by thorp...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f050f06e8823
branches:  netbsd-1-5
changeset: 488933:f050f06e8823
user:      mrg <mrg%NetBSD.org@localhost>
date:      Mon Aug 07 00:59:49 2000 +0000

description:
pull up 1.3 (approved by thorpej):
>Revamp cache flush routines.

diffstat:

 sys/arch/sparc64/sparc64/cache.c |  20 +++++++++++---------
 sys/arch/sparc64/sparc64/cache.h |  12 ++++++++----
 2 files changed, 19 insertions(+), 13 deletions(-)

diffs (94 lines):

diff -r 746b33c1a817 -r f050f06e8823 sys/arch/sparc64/sparc64/cache.c
--- a/sys/arch/sparc64/sparc64/cache.c  Mon Aug 07 00:58:10 2000 +0000
+++ b/sys/arch/sparc64/sparc64/cache.c  Mon Aug 07 00:59:49 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.2 1998/09/05 23:57:26 eeh Exp $ */
+/*     $NetBSD: cache.c,v 1.2.22.1 2000/08/07 00:59:49 mrg Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -54,6 +54,8 @@
 /*
  * Cache routines.
  *
+ * UltraSPARC has VIPT D$ and PIPT I$.
+ *
  * TODO:
  *     - rework range flush
  */
@@ -91,8 +93,8 @@
  * To get the E$ we read to each cache line.  
  */
 int
-cache_flush_page(va)
-       vaddr_t va;
+cache_flush_page(pa)
+       paddr_t pa;
 {
        register int i, j, ls;
        register char *p;
@@ -100,20 +102,20 @@
 
 #ifdef DEBUG
        if (cachedebug)
-               printf("cache_flush_page %p\n", va);
-       if (va & PGOFSET)
-               panic("cache_flush_page: asked to flush misaligned va %x",va);
+               printf("cache_flush_page %llx\n", pa);
+       if (pa & PGOFSET)
+               panic("cache_flush_page: asked to flush misaligned pa %llx", pa);
 #endif
 
        /* Don't flush if not enabled or not probed. */
        if (!cacheinfo.c_enabled) return 0;
 
        cachestats.cs_npgflush++;
-       p = (char *)va;
+       p = (char *)(u_long)pa;
        ls = cacheinfo.c_linesize;
        i = NBPG >> cacheinfo.dc_l2linesize;
        /* Assume E$ takes care of itself*/
-       kp = (int *)((va & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
+       kp = (int *)((pa & (cacheinfo.ec_totalsize - 1)) + KERNBASE);
        j = 0; /* defeat optimizer? */
        for (; --i >= 0; p += ls) {
                flush(p);       /* Take care of I$. */
@@ -136,7 +138,7 @@
 
 int
 cache_flush(base, len)
-       caddr_t base;
+       vaddr_t base;
        size_t len;
 {
        int i, j, ls;
diff -r 746b33c1a817 -r f050f06e8823 sys/arch/sparc64/sparc64/cache.h
--- a/sys/arch/sparc64/sparc64/cache.h  Mon Aug 07 00:58:10 2000 +0000
+++ b/sys/arch/sparc64/sparc64/cache.h  Mon Aug 07 00:59:49 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.h,v 1.2 1998/09/05 23:57:26 eeh Exp $ */
+/*     $NetBSD: cache.h,v 1.2.22.1 2000/08/07 00:59:51 mrg Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -135,13 +135,17 @@
  * Routines for dealing with the cache.
  */
 void   cache_enable __P((void));               /* turn it on */
-int    cache_flush_page __P((vaddr_t va));     /* flush page from E$ */
-int    cache_flush __P((caddr_t, size_t));     /* flush region */
+int    cache_flush_page __P((paddr_t));        /* flush page from E$ */
+int    cache_flush __P((vaddr_t, vsize_t));    /* flush region */
 
 /* The following two are for I$ and D$ flushes and are in locore.s */
-void   dcache_flush_page __P((vaddr_t va));    /* flush page from D$ */
+void   dcache_flush_page __P((paddr_t));       /* flush page from D$ */
 void   blast_vcache __P((void));               /* Clear entire contents of I$ and D$ */
 
+/* The following flush a range from the D$ and I$ but not E$. */
+void   cache_flush_virt __P((vaddr_t, vsize_t));
+void   cache_flush_phys __P((paddr_t, psize_t, int));
+
 /*
  * Cache control information.
  */