[src/trunk]: src/sys/arch fix missing SCI IRQ mask/unmask code.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/990199e33561
branches:  trunk
changeset: 479924:990199e33561
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Dec 27 10:50:41 1999 +0000

description:
fix missing SCI IRQ mask/unmask code.

diffstat:

 sys/arch/evbsh3/evbsh3/shb.c |  11 +++++++----
 sys/arch/sh3/include/intr.h  |  16 +++++++++++++++-
 2 files changed, 22 insertions(+), 5 deletions(-)

diffs (61 lines):

diff -r 432073c62ab3 -r 990199e33561 sys/arch/evbsh3/evbsh3/shb.c
--- a/sys/arch/evbsh3/evbsh3/shb.c      Mon Dec 27 10:20:59 1999 +0000
+++ b/sys/arch/evbsh3/evbsh3/shb.c      Mon Dec 27 10:50:41 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: shb.c,v 1.4 1999/12/06 14:10:49 msaitoh Exp $  */
+/*     $NetBSD: shb.c,v 1.5 1999/12/27 10:50:41 msaitoh Exp $  */
 
 /*-
  * Copyright (c) 1993, 1994 Charles Hannum.  All rights reserved.
@@ -403,9 +403,11 @@
        if (irl >= INTEVT_SOFT) {
                /* This is software interrupt */
                irq_num = (irl - INTEVT_SOFT);
-       } else if (irl == INTEVT_TMU1)
+       } else if (irl == INTEVT_TMU1) {
                irq_num = TMU1_IRQ;
-       else
+       } else if (IS_INTEVT_SCI0(irl)) {       /* XXX TOO DIRTY */
+               irq_num = SCI_IRQ;
+       } else
                irq_num = (irl - 0x200) >> 5;
 
        mask_irq(irq_num);
@@ -524,7 +526,8 @@
 }
 
 void
-unmask_irq(int irq)
+unmask_irq(irq)
+       int irq;
 {
 
        switch (irq) {
diff -r 432073c62ab3 -r 990199e33561 sys/arch/sh3/include/intr.h
--- a/sys/arch/sh3/include/intr.h       Mon Dec 27 10:20:59 1999 +0000
+++ b/sys/arch/sh3/include/intr.h       Mon Dec 27 10:50:41 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intr.h,v 1.2 1999/09/14 10:22:35 tsubai Exp $  */
+/*     $NetBSD: intr.h,v 1.3 1999/12/27 10:50:41 msaitoh Exp $ */
 
 /*
  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
@@ -170,4 +170,18 @@
 #define INTEVT_TMU1 0x420
 #define INTEVT_TMU2 0x440
 
+#define INTEVT_SCI0_ERI        0x4e0
+#define INTEVT_SCI0_RXI        0x500
+#define INTEVT_SCI0_TXI        0x520
+#define INTEVT_SCI0_TEI        0x540
+
+#define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \
+                       || (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI))
+
+#define        INTEVT_PRI      0x4a0   /* Periodic interrupt generated by RTC */
+
+#if defined(SH4)
+#define        INTEVT_SCIF     0x700
+#endif
+
 #endif /* !_SH3_INTR_H_ */