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[src/trunk]: src/sys/arch/sparc64/sparc64 Prevent the system from getting wat...
details: https://anonhg.NetBSD.org/src/rev/be6d53f68948
branches: trunk
changeset: 485069:be6d53f68948
user: eeh <eeh%NetBSD.org@localhost>
date: Tue Apr 18 02:12:25 2000 +0000
description:
Prevent the system from getting watchdog reset by returning directly to user
mode if restoring the user window traps. Also reduce the time we run with
%tl>0.
diffstat:
sys/arch/sparc64/sparc64/locore.s | 318 +++++++++++++++++++++++--------------
1 files changed, 196 insertions(+), 122 deletions(-)
diffs (truncated from 651 to 300 lines):
diff -r b718ccd9a829 -r be6d53f68948 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Tue Apr 18 02:07:57 2000 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Tue Apr 18 02:12:25 2000 +0000
@@ -1,11 +1,13 @@
-/* $NetBSD: locore.s,v 1.54 2000/04/13 18:40:27 eeh Exp $ */
+/* $NetBSD: locore.s,v 1.55 2000/04/18 02:12:25 eeh Exp $ */
/*
* Copyright (c) 1996-1999 Eduardo Horvath
* Copyright (c) 1996 Paul Kranenburg
* Copyright (c) 1996
- * The President and Fellows of Harvard College. All rights reserved.
+ * The President and Fellows of Harvard College.
+ * All rights reserved.
* Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
+ * The Regents of the University of California.
+ * All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
@@ -24,45 +26,47 @@
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
+ * documentation and/or other materials provided with the
+ * distribution.
+ * 3. All advertising materials mentioning features or use of this
+ * software must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* This product includes software developed by Harvard University.
* This product includes software developed by Paul Kranenburg.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 4. Neither the name of the University nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
*
* @(#)locore.s 8.4 (Berkeley) 12/10/93
*/
#undef NO_VCACHE /* Map w/D$ disabled */
-#define TRAPTRACE /* Keep history of all traps (may watchdog) */
-#undef FLTRACE /* Keep history of all page faults only */
+#define TRAPTRACE /* Keep history of all traps (unsafe) */
+#undef FLTRACE /* Keep history of all page faults */
#define TRAPSTATS /* Count traps */
-#undef TRAPS_USE_IG /* Use Interrupt Globals for trap handling */
+#undef TRAPS_USE_IG /* Use Interrupt Globals for all traps */
#undef LOCKED_PCB /* Lock current proc's PCB in MMU */
-#define HWREF /* Handle ref/mod tracking in trap handlers */
-#undef MMUDEBUG /* Check use of MMU regs during MMU faults */
+#define HWREF /* Track ref/mod bits in trap handlers */
+#undef MMUDEBUG /* Check use of regs during MMU faults */
#define VECTORED_INTERRUPTS /* Use interrupt vectors */
#define PMAP_FPSTATE /* Allow nesting of VIS pmap copy/zero */
#define NEW_FPSTATE
-#define PMAP_PHYS_PAGE /* Don't use block ld/st for pmap copy/zero */
-#define DCACHE_BUG /* Clear D$ line before loads from ASI_PHYS */
+#define PMAP_PHYS_PAGE /* Use phys ASIs for pmap copy/zero */
+#define DCACHE_BUG /* Flush D$ around ASI_PHYS accesses */
#define NO_TSB /* Don't use TSB */
#undef TICK_IS_TIME /* Keep %tick synchronized with time */
@@ -149,8 +153,8 @@
/*
* GNU assembler does not understand `.empty' directive; Sun assembler
* gripes about labels without it. To allow cross-compilation using
- * the Sun assembler, and because .empty directives are useful documentation,
- * we use this trick.
+ * the Sun assembler, and because .empty directives are useful
+ * documentation, we use this trick.
*/
#ifdef SUN_AS
#define EMPTY .empty
@@ -298,12 +302,14 @@
.space KGDB_STACK_SIZE ! hope this is enough
#endif
-/*
- * This is an emergency stack used when we overflow the normal kernel stack.
+#ifdef DEBUG
+/*
+ * This stack is used when we detect kernel stack corruption.
*/
.space USPACE
.align 16
panicstack:
+#endif
/*
* _cpcb points to the current pcb (and hence u. area).
@@ -330,8 +336,8 @@
.word 1
/*
* _cpumod is the current cpu model, used to distinguish between variants
- * in the Sun4 and Sun4M families. See /sys/arch/sparc64/include/param.h for
- * possible values.
+ * in the Sun4 and Sun4M families. See /sys/arch/sparc64/include/param.h
+ * for possible values.
*/
.globl _C_LABEL(cpumod)
_C_LABEL(cpumod):
@@ -385,7 +391,8 @@
* the window overflow, underflow, and clean window traps which are
* 32 instructions long, large enough to in-line.
*
- * The spitfire CPU (Ultra I) has 4 different sets of global registers. (blah blah...)
+ * The spitfire CPU (Ultra I) has 4 different sets of global registers.
+ * (blah blah...)
*
* I used to generate these numbers by address arithmetic, but gas's
* expression evaluator has about as much sense as your average slug
@@ -396,9 +403,9 @@
* Hardware interrupt vectors can be `linked'---the linkage is to regular
* C code---or rewired to fast in-window handlers. The latter are good
* for unbuffered hardware like the Zilog serial chip and the AMD audio
- * chip, where many interrupts can be handled trivially with pseudo-DMA or
- * similar. Only one `fast' interrupt can be used per level, however, and
- * direct and `fast' interrupts are incompatible. Routines in intr.c
+ * chip, where many interrupts can be handled trivially with pseudo-DMA
+ * or similar. Only one `fast' interrupt can be used per level, however,
+ * and direct and `fast' interrupts are incompatible. Routines in intr.c
* handle setting these, with optional paranoia.
*/
@@ -419,57 +426,70 @@
/* regular vectored traps */
#ifdef DEBUG
#ifdef TRAPTRACE
-#define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit; or %g1, %lo(1f), %g1; 1:
+#define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(1f), %g1; 1:
#if 0
-#define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin; or %l6, %lo(9f), %l6; 9:
+#define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin;\
+ or %l6, %lo(9f), %l6; 9:
#endif
#ifdef TRAPS_USE_IG
-#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate; sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
+#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate;\
+ sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
#else
-#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate; sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
+#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate;\
+ sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
#endif
#define TRACERELOAD32 ba reload32; nop;
#define TRACERELOAD64 ba reload64; nop;
#define TRACEFLT TRACEME
#define VTRAP(type, label) \
- sethi %hi(label), %g1; ba,pt %icc,traceit; or %g1, %lo(label), %g1; NOTREACHED; TA8
+ sethi %hi(label), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(label), %g1; NOTREACHED; TA8
#else
#define TRACEME
#define TRACEWIN TRACEME
#define TRACERELOAD32
#define TRACERELOAD64
#ifdef FLTRACE
-#define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit; or %g1, %lo(1f), %g1; 1:
+#define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(1f), %g1; 1:
#else
#define TRACEFLT TRACEME
#endif
#define VTRAP(type, label) \
- sethi KERNBASE,%g1; rdpr %tt,%g2; or %g1,0x28,%g1; b label; stx %g2,[%g1]; NOTREACHED; TA8
+ sethi KERNBASE,%g1; rdpr %tt,%g2; or %g1,0x28,%g1; b label;\
+ stx %g2,[%g1]; NOTREACHED; TA8
#endif
#else
#ifdef TRAPTRACE
-#define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit; or %g1, %lo(1f), %g1; 1:
+#define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(1f), %g1; 1:
#if 0
- /* Can't use this macro 'cause we have no clean registers during a spill */
-#define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin; or %l6, %lo(9f), %l6; 9:
+/* Can't use this 'cause we have no clean registers during a spill */
+#define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin;\
+ or %l6, %lo(9f), %l6; 9:
#endif
#ifdef TRAPS_USE_IG
-#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate; sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
+#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate;\
+ sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
#else
-#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate; sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
+#define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate;\
+ sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9:
#endif
#define TRACERELOAD32 ba reload32; nop;
#define TRACERELOAD64 ba reload64; nop;
#define TRACEFLT TRACEME
#define VTRAP(type, label) \
- sethi %hi(label), %g1; ba,pt %icc,traceit; or %g1, %lo(label), %g1; NOTREACHED; TA8
+ sethi %hi(label), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(label), %g1; NOTREACHED; TA8
#else
#define TRACEME
#define TRACEWIN TRACEME
#define TRACERELOAD32
#define TRACERELOAD64
#ifdef FLTRACE
-#define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit; or %g1, %lo(1f), %g1; 1:
+#define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit;\
+ or %g1, %lo(1f), %g1; 1:
#else
#define TRACEFLT TRACEME
#endif
@@ -508,10 +528,9 @@
#define BPT_KGDB_EXEC TRAP(T_KGDB_EXEC)
#endif
-/* special high-speed 1-instruction-shaved-off traps (get nothing in %l3) */
#define SYSCALL VTRAP(0x100, syscall_setup)
#ifdef notyet
-#define ZS_INTERRUPT b zshard; nop; TA8
+#define ZS_INTERRUPT ba,a,pt %icc, zshard; nop; TA8
#else
#define ZS_INTERRUPT4U HARDINT4U(12)
#endif
@@ -592,7 +611,7 @@
#define SPILLBOTH(label64,label32,as) \
TRACEWIN; \
andcc %sp, 1, %g0; \
- bnz,pt %xcc, label64+4; /* See if it's a v9 stack or v8 */ \
+ bnz,pt %xcc, label64+4; /* Is it a v9 or v8 stack? */ \
wr %g0, as, %asi; \
ba,pt %xcc, label32+8; \
srl %sp, 0, %sp; /* fixup 32-bit pointers */ \
@@ -672,9 +691,6 @@
.globl start, _C_LABEL(kernel_text)
_C_LABEL(kernel_text) = start ! for kvm_mkdb(8)
start:
-/*
- * Put sun4u traptable first, since it needs the most stringent aligment (32K)
- */
/* Traps from TL=0 -- traps from user mode */
#define TABLE user_
.globl _C_LABEL(trapbase)
@@ -682,13 +698,13 @@
b dostart; nop; TA8 ! 000 = reserved -- Use it to boot
/* We should not get the next 5 traps */
UTRAP(0x001) ! 001 = POR Reset -- ROM should get this
- UTRAP(0x002) ! 002 = WDR Watchdog -- ROM should get this
+ UTRAP(0x002) ! 002 = WDR -- ROM should get this
UTRAP(0x003) ! 003 = XIR -- ROM should get this
UTRAP(0x004) ! 004 = SIR -- ROM should get this
UTRAP(0x005) ! 005 = RED state exception
UTRAP(0x006); UTRAP(0x007)
VTRAP(T_INST_EXCEPT, textfault) ! 008 = instr. access exept
- VTRAP(T_TEXTFAULT, textfault) ! 009 = instr access MMU miss -- no MMU
+ VTRAP(T_TEXTFAULT, textfault) ! 009 = instr access MMU miss
VTRAP(T_INST_ERROR, textfault) ! 00a = instr. access err
UTRAP(0x00b); UTRAP(0x00c); UTRAP(0x00d); UTRAP(0x00e); UTRAP(0x00f)
TRAP(T_ILLINST) ! 010 = illegal instruction
@@ -766,7 +782,7 @@
TRAP(T_PA_WATCHPT) ! 061 = physical address data watchpoint
TRAP(T_VA_WATCHPT) ! 062 = virtual address data watchpoint
UTRAP(T_ECCERR) ! We'll implement this one later
-ufast_IMMU_miss: ! 063 = fast instr access MMU miss
+ufast_IMMU_miss: ! 064 = fast instr access MMU miss
TRACEFLT ! DEBUG
ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
ldxa [%g0] ASI_IMMU, %g1 ! Hard coded for unified 8K TSB Load IMMU tag target register
@@ -1039,7 +1055,7 @@
TRAP(T_PA_WATCHPT) ! 061 = physical address data watchpoint
TRAP(T_VA_WATCHPT) ! 062 = virtual address data watchpoint
UTRAP(T_ECCERR) ! We'll implement this one later
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