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[src/trunk]: src/sys/arch/mips/mips Make SOFTFLOAT emulation compatible with ...
details: https://anonhg.NetBSD.org/src/rev/131aa34a2099
branches: trunk
changeset: 479985:131aa34a2099
user: castor <castor%NetBSD.org@localhost>
date: Wed Dec 29 04:41:12 1999 +0000
description:
Make SOFTFLOAT emulation compatible with _MIPS_BSD_API_LP32_64CLEAN
diffstat:
sys/arch/mips/mips/fp.S | 632 ++++++++++++++++++++++++++-----------------
sys/arch/mips/mips/locore.S | 10 +-
2 files changed, 382 insertions(+), 260 deletions(-)
diffs (truncated from 1035 to 300 lines):
diff -r 03e2929c0e50 -r 131aa34a2099 sys/arch/mips/mips/fp.S
--- a/sys/arch/mips/mips/fp.S Wed Dec 29 04:16:21 1999 +0000
+++ b/sys/arch/mips/mips/fp.S Wed Dec 29 04:41:12 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fp.S,v 1.15 1999/12/22 04:54:15 jun Exp $ */
+/* $NetBSD: fp.S,v 1.16 1999/12/29 04:41:13 castor Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -76,6 +76,14 @@
#define COND_LESS 0x4
#define COND_SIGNAL 0x8
+#if SZREG == 8
+#define SZREG_SHFT 3
+#define SZREG_MASK 0x00f8
+#else
+#define SZREG_SHFT 2
+#define SZREG_MASK 0x007c
+#endif
+
/*----------------------------------------------------------------------------
*
* MachEmulateFP --
@@ -470,21 +478,24 @@
lw v0, U_PCB_FPREGS+FRAME_FP0(t0)
- srl t0, a0, 16-2
- andi t0, t0, 0x007C
+ srl t0, a0, 16-SZREG_SHFT
+ andi t0, t0, SZREG_MASK
addu t0, t0, a1
- sw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_S v0, FRAME_ZERO(t0)
+ REG_EPILOGUE
b done
mtoc1:
- sw zero, FRAME_ZERO(a1) # ensure zero has value 0
-
- srl t0, a0, 16-2
- andi t0, t0, 0x007C
+ REG_PROLOGUE
+ REG_S zero, FRAME_ZERO(a1) # ensure zero has value 0
+ srl t0, a0, 16-SZREG_SHFT
+ andi t0, t0, SZREG_MASK
addu v0, a1, t0
- lw v0, FRAME_ZERO(v0)
+ REG_L v0, FRAME_ZERO(v0)
+ REG_EPILOGUE
lw t0, _C_LABEL(fpcurproc)
srl t1, a0, 11-2
@@ -509,27 +520,33 @@
cfinvalid:
- srl t0, a0, 16-2
- andi t0, t0, 0x007C
+ srl t0, a0, 16-SZREG_SHFT
+ andi t0, t0, SZREG_MASK
addu t0, t0, a1
- sw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_S v0, FRAME_ZERO(t0)
+ REG_EPILOGUE
b done
ctoc1:
- sw zero, FRAME_ZERO(a1) # ensure zero has value 0
+ REG_PROLOGUE
+ REG_S zero, FRAME_ZERO(a1) # ensure zero has value 0
+ REG_EPILOGUE
srl t0, a0, 11
andi t0, t0, 0x001F
li t1, 0x1F
bne t0, t1, done
- srl t0, a0, 16-2
- andi t0, t0, 0x007C
+ srl t0, a0, 16-SZREG_SHFT
+ andi t0, t0, SZREG_MASK
addu v0, a1, t0
lw t0, _C_LABEL(fpcurproc)
- lw v0, FRAME_ZERO(v0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(v0)
+ REG_EPILOGUE
lw t0, P_ADDR(t0) # get pointer to pcb for proc
sw v0, U_PCB_FPREGS+FRAME_FSR(t0)
@@ -592,23 +609,29 @@
li v0, MIPS_FPU_COND_BIT
and v0, v0, a2
beq v0, zero, bcemul_branch
- lw v0, FRAME_EPC(a1)
+ REG_PROLOGUE
+ REG_L v0, FRAME_EPC(a1)
addiu v0, v0, 4
- sw v0, FRAME_EPC(a1)
+ REG_S v0, FRAME_EPC(a1)
+ REG_EPILOGUE
b done
bctrue_l:
li v0, MIPS_FPU_COND_BIT
and v0, v0, a2
bne v0, zero, bcemul_branch
- lw v0, FRAME_EPC(a1)
+ REG_PROLOGUE
+ REG_L v0, FRAME_EPC(a1)
addiu v0, v0, 4
- sw v0, FRAME_EPC(a1)
+ REG_S v0, FRAME_EPC(a1)
+ REG_EPILOGUE
b done
bcemul_branch:
/* Fetch delay slot instruction */
sw a1, CALLFRAME_SIZ + 4(sp)
- lw a0, FRAME_EPC(a1)
+ REG_PROLOGUE
+ REG_L a0, FRAME_EPC(a1)
+ REG_EPILOGUE
addiu a0, a0, 4
jal _C_LABEL(fuiword)
@@ -2359,7 +2382,9 @@
* so compute the next PC.
*/
lw t0, CALLFRAME_SIZ + 8(sp)
- lw v0, FRAME_EPC(a1)
+ REG_PROLOGUE
+ REG_L v0, FRAME_EPC(a1)
+ REG_EPILOGUE
bgez t0, 1f # Check the branch delay bit.
/*
* The instruction is in the branch delay slot so the branch will have to
@@ -2381,7 +2406,9 @@
1:
addiu v0, v0, 4 # v0 = next pc
2:
- sw v0, FRAME_EPC(a1) # save new pc
+ REG_PROLOGUE
+ REG_S v0, FRAME_EPC(a1) # save new pc
+ REG_EPILOGUE
lw ra, CALLFRAME_RA(sp)
addu sp, sp, CALLFRAME_SIZ
@@ -3939,7 +3966,9 @@
* It should be used to emulate instruction in branch delay slot.
*/
LEAF(bcemul_delay_slot)
- sw zero, FRAME_ZERO(a1) # ensure zero has value 0
+ REG_PROLOGUE
+ REG_S zero, FRAME_ZERO(a1) # ensure zero has value 0
+ REG_EPILOGUE
srl t0, a0, 26-2
andi t0, t0, 0x00FC
@@ -4088,15 +4117,17 @@
.text
bcemul_addi:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
sll t2, a0, 16
sra t2, t2, 16
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(t0)
+ REG_EPILOGUE
addu t0, v0, t2
/* Overflow check */
@@ -4111,299 +4142,353 @@
j _C_LABEL(bcemul_sigfpe)
addiok:
- sw t0, FRAME_ZERO(t1)
+ REG_PROLOGUE
+ REG_S t0, FRAME_ZERO(t1)
+ REG_EPILOGUE
b bcemul_done
bcemul_addiu:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
sll t2, a0, 16
sra t2, t2, 16
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(t0)
addu v0, v0, t2
- sw v0, FRAME_ZERO(t1)
+ REG_S v0, FRAME_ZERO(t1)
+ REG_EPILOGUE
b bcemul_done
bcemul_slti:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
sll t2, a0, 16
sra t2, t2, 16
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(t0)
slt v0, v0, t2
- sw v0, FRAME_ZERO(t1)
+ REG_S v0, FRAME_ZERO(t1)
+ REG_EPILOGUE
b bcemul_done
bcemul_sltiu:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
sll t2, a0, 16
sra t2, t2, 16
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(t0)
sltu v0, v0, t2
- sw v0, FRAME_ZERO(t1)
+ REG_S v0, FRAME_ZERO(t1)
+ REG_EPILOGUE
b bcemul_done
bcemul_andi:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
andi t2, a0, 0xFFFF
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
+ REG_L v0, FRAME_ZERO(t0)
and v0, v0, t2
- sw v0, FRAME_ZERO(t1)
+ REG_S v0, FRAME_ZERO(t1)
+ REG_EPILOGUE
b bcemul_done
bcemul_ori:
- srl t0, a0, 21-2 # rs
- srl t1, a0, 16-2 # rt
- andi t0, t0, 0x007C
- andi t1, t1, 0x007C
+ srl t0, a0, 21-SZREG_SHFT # rs
+ srl t1, a0, 16-SZREG_SHFT # rt
+ andi t0, t0, SZREG_MASK
+ andi t1, t1, SZREG_MASK
addu t0, a1, t0
addu t1, a1, t1
andi t2, a0, 0xFFFF
- lw v0, FRAME_ZERO(t0)
+ REG_PROLOGUE
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