[src/netbsd-1-5]: src/sys/dev/tc Pull up revision 1.3 (requested by perseant):

[jhawk <jhawk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b12adaf30009
branches:  netbsd-1-5
changeset: 490440:b12adaf30009
user:      jhawk <jhawk%NetBSD.org@localhost>
date:      Tue Dec 26 15:58:02 2000 +0000

description:
Pull up revision 1.3 (requested by perseant):
  Make XalphaNetBSD compile with SFB support.

diffstat:

 sys/dev/tc/sfbreg.h |  51 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 50 insertions(+), 1 deletions(-)

diffs (69 lines):

diff -r 08376d1c632a -r b12adaf30009 sys/dev/tc/sfbreg.h
--- a/sys/dev/tc/sfbreg.h       Tue Dec 26 15:51:54 2000 +0000
+++ b/sys/dev/tc/sfbreg.h       Tue Dec 26 15:58:02 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sfbreg.h,v 1.2 1999/10/20 02:44:48 nisimura Exp $ */
+/* $NetBSD: sfbreg.h,v 1.2.6.1 2000/12/26 15:58:02 jhawk Exp $ */
 
 /*
  * Copyright (c) 1996 Carnegie-Mellon University.
@@ -35,6 +35,9 @@
  * All definitions are in "dense" TURBOchannel space.
  */
 
+#ifndef _DEV_TC_SFBREG_H_
+#define _DEV_TC_SFBREG_H_
+
 /*
  * Size of the SFB address space.
  */
@@ -86,3 +89,49 @@
 #define        SFB_ASIC_ENABLE_INTR    0x0074  /* Enable/Disable Interrupts (W) */
 #define        SFB_ASIC_TCCLK          0x0078  /* TCCLK count (R/W) */
 #define        SFB_ASIC_VIDCLK         0x007c  /* VIDCLK count (R/W) */
+
+/*
+ * Same as above but in 32-bit units, and named like the corrseponding
+ * TGA registers, for easy comparison.
+ */
+typedef u_int32_t sfb_reg_t;
+
+#define        SFB_REG_GCBR0   0x000           /* Copy buffer 0 */
+#define        SFB_REG_GCBR1   0x001           /* Copy buffer 1 */
+#define        SFB_REG_GCBR2   0x002           /* Copy buffer 2 */
+#define        SFB_REG_GCBR3   0x003           /* Copy buffer 3 */
+#define        SFB_REG_GCBR4   0x004           /* Copy buffer 4 */
+#define        SFB_REG_GCBR5   0x005           /* Copy buffer 5 */
+#define        SFB_REG_GCBR6   0x006           /* Copy buffer 6 */
+#define        SFB_REG_GCBR7   0x007           /* Copy buffer 7 */
+
+#define        SFB_REG_GFGR    0x008           /* Foreground */
+#define        SFB_REG_GBGR    0x009           /* Background */
+#define        SFB_REG_GPMR    0x00a           /* Plane Mask */
+#define        SFB_REG_GPXR_S  0x00b           /* Pixel Mask (one-shot) */
+#define        SFB_REG_GMOR    0x00c           /* Mode */
+#define        SFB_REG_GOPR    0x00d           /* Raster Operation */
+#define        SFB_REG_GPSR    0x00e           /* Pixel Shift */
+#define        SFB_REG_GADR    0x00f           /* Address */
+
+#define        SFB_REG_GB1R    0x010           /* Bresenham 1 */
+#define        SFB_REG_GB2R    0x011           /* Bresenham 2 */
+#define        SFB_REG_GB3R    0x012           /* Bresenham 3 */
+
+#define        SFB_REG_GCTR    0x013           /* Continue */
+#define        SFB_REG_GDER    0x014           /* Deep */
+#define SFB_REG_GREV   0x015           /* Start/Version on SFB,
+
+                                        * Revision on SFB2 */
+#define SFB_REG_CINT   0x016           /* Clear Interrupt */
+/* 0x017 - unused */
+#define SFB_REG_VRFR   0x018           /* Video Refresh */
+#define        SFB_REG_VHCR    0x019           /* Horizontal Control */
+#define        SFB_REG_VVCR    0x01a           /* Vertical Control */
+#define        SFB_REG_VVBR    0x01b           /* Video Base Address */
+#define        SFB_REG_VVVR    0x01c           /* Video Valid */
+#define        SFB_REG_SISR    0x01d           /* Enable/Disable Interrupts */
+#define        SFB_REG_TCCLK   0x01e           /* TCCLK count (R/W) */
+#define        SFB_REG_VIDCLK  0x01f           /* VIDCLK count (R/W) */
+
+#endif /* _DEV_TC_SFBREG_H_ */