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[src/netbsd-1-5]: src/sys/arch/mips/include Pull up revision 1.35 (approved b...
details: https://anonhg.NetBSD.org/src/rev/fbe7b7ac07dc
branches: netbsd-1-5
changeset: 488588:fbe7b7ac07dc
user: jeffs <jeffs%NetBSD.org@localhost>
date: Wed Jul 19 18:21:22 2000 +0000
description:
Pull up revision 1.35 (approved by thorpej):
if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately. This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.
diffstat:
sys/arch/mips/include/cpuregs.h | 13 ++++++++++---
1 files changed, 10 insertions(+), 3 deletions(-)
diffs (37 lines):
diff -r d2fbb5500932 -r fbe7b7ac07dc sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Wed Jul 19 17:40:39 2000 +0000
+++ b/sys/arch/mips/include/cpuregs.h Wed Jul 19 18:21:22 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.34 2000/06/09 06:06:59 soda Exp $ */
+/* $NetBSD: cpuregs.h,v 1.34.2.1 2000/07/19 18:21:22 jeffs Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -197,6 +197,8 @@
#define MIPS3_SR_FR_32 0x04000000
#define MIPS3_SR_RE 0x02000000
+#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
+#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
#define MIPS3_SR_DIAG_BEV 0x00400000
#define MIPS3_SR_SOFT_RESET 0x00100000
#define MIPS3_SR_DIAG_CH 0x00040000
@@ -244,11 +246,16 @@
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
- * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
+ * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
+ * choose to enable this interrupt.
*/
+#if defined(MIPS3_ENABLE_CLOCK_INTR)
+#define MIPS3_INT_MASK MIPS_INT_MASK
+#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
+#else
#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
-
+#endif
/*
* The bits in the context register.
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