[src/netbsd-1-5]: src/sys/dev/ic Pull up revisions 1.24-1.25 (requested by mj...

[he <he%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/56d7657d853a
branches:  netbsd-1-5
changeset: 490886:56d7657d853a
user:      he <he%NetBSD.org@localhost>
date:      Fri Mar 16 19:16:29 2001 +0000

description:
Pull up revisions 1.24-1.25 (requested by mjacob):
  Put in offset definitions for FPM and FBM registers, plus just
  enough bits defined so we can reset them.  Add maintenance note.

diffstat:

 sys/dev/ic/ispreg.h |  38 +++++++++++++++++++++++++++-----------
 1 files changed, 27 insertions(+), 11 deletions(-)

diffs (63 lines):

diff -r 43f76493aef4 -r 56d7657d853a sys/dev/ic/ispreg.h
--- a/sys/dev/ic/ispreg.h       Fri Mar 16 19:15:57 2001 +0000
+++ b/sys/dev/ic/ispreg.h       Fri Mar 16 19:16:29 2001 +0000
@@ -1,18 +1,17 @@
-/* $NetBSD: ispreg.h,v 1.20.4.1 2000/08/28 17:45:11 mjacob Exp $ */
+/* $NetBSD: ispreg.h,v 1.20.4.2 2001/03/16 19:16:29 he Exp $ */
 /*
  * This driver, which is contained in NetBSD in the files:
  *
  *     sys/dev/ic/isp.c
- *     sys/dev/ic/ic/isp.c
- *     sys/dev/ic/ic/isp_inline.h
- *     sys/dev/ic/ic/isp_netbsd.c
- *     sys/dev/ic/ic/isp_netbsd.h
- *     sys/dev/ic/ic/isp_target.c
- *     sys/dev/ic/ic/isp_target.h
- *     sys/dev/ic/ic/isp_tpublic.h
- *     sys/dev/ic/ic/ispmbox.h
- *     sys/dev/ic/ic/ispreg.h
- *     sys/dev/ic/ic/ispvar.h
+ *     sys/dev/ic/isp_inline.h
+ *     sys/dev/ic/isp_netbsd.c
+ *     sys/dev/ic/isp_netbsd.h
+ *     sys/dev/ic/isp_target.c
+ *     sys/dev/ic/isp_target.h
+ *     sys/dev/ic/isp_tpublic.h
+ *     sys/dev/ic/ispmbox.h
+ *     sys/dev/ic/ispreg.h
+ *     sys/dev/ic/ispvar.h
  *     sys/microcode/isp/asm_sbus.h
  *     sys/microcode/isp/asm_1040.h
  *     sys/microcode/isp/asm_1080.h
@@ -385,6 +384,19 @@
 #define        MAX_MAILBOX     8
 
 /*
+ * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
+ * NB: The RISC processor must be paused and the appropriate register
+ * bank selected via BIU2100_CSR bits.
+ */
+
+#define        FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
+#define                FPM_SOFT_RESET          0x0100
+
+#define        FBM_CMD         (BIU_BLOCK + 0xB8)
+#define                FBMCMD_FIFO_RESET_ALL   0xA000
+
+
+/*
  * SXP Block Register Offsets
  */
 #define        SXP_PART_ID     (SXP_BLOCK+0x0)         /* R  : Part ID Code */
@@ -636,6 +648,10 @@
 #define        HCCR_CMD_PAUSE                  0x2000  /* Pause RISC */
 #define        HCCR_CMD_RELEASE                0x3000  /* Release Paused RISC */
 #define        HCCR_CMD_STEP                   0x4000  /* Single Step RISC */
+#define        HCCR_2X00_DISABLE_PARITY_PAUSE  0x4001  /*
+                                                * Disable RISC pause on FPM
+                                                * parity error.
+                                                */
 #define        HCCR_CMD_SET_HOST_INT           0x5000  /* Set Host Interrupt */
 #define        HCCR_CMD_CLEAR_HOST_INT         0x6000  /* Clear Host Interrupt */
 #define        HCCR_CMD_CLEAR_RISC_INT         0x7000  /* Clear RISC interrupt */