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[src/trunk]: src/sys/arch/mips/mips put cache op #defines up at the top of th...
details: https://anonhg.NetBSD.org/src/rev/14f89a6681bc
branches: trunk
changeset: 488046:14f89a6681bc
user: cgd <cgd%NetBSD.org@localhost>
date: Sat Jun 17 01:35:28 2000 +0000
description:
put cache op #defines up at the top of the file, so all cache ops can
use them. Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think... Finally,
actually use them for every bloody cache op.
diffstat:
sys/arch/mips/mips/locore_mips3.S | 236 +++++++++++++++++++------------------
1 files changed, 124 insertions(+), 112 deletions(-)
diffs (truncated from 403 to 300 lines):
diff -r 0565e7381ce9 -r 14f89a6681bc sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Sat Jun 17 01:20:50 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Sat Jun 17 01:35:28 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.34 2000/06/09 06:07:01 soda Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.35 2000/06/17 01:35:28 cgd Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -114,6 +114,30 @@
*/
/*
+ * XXX mips/include
+ */
+#define C_IINV_I 0x00
+#define C_IWBINV_D 0x01
+#define C_IINV_SI 0x02
+#define C_IWBINV_SD 0x03
+
+#define C_ILDTAG_I 0x04
+#define C_ILDTAG_D 0x05
+#define C_ILDTAG_SI 0x06
+#define C_ILDTAG_SD 0x07
+
+#define C_HINV_I 0x10
+#define C_HINV_D 0x11
+#define C_HINV_SI 0x12
+#define C_HINV_SD 0x13
+
+#define C_HWBINV_D 0x15
+#define C_HWBINV_SD 0x17
+
+#define C_HSETV_SI 0x1e
+#define C_HSETV_SD 0x1f
+
+/*
*============================================================================
*
* MIPS III ISA support, part 1: locore exception vectors.
@@ -1473,14 +1497,14 @@
addu t1, t0, t1 # End address
subu t1, t1, 128
1:
- cache 0, 0(t0)
- cache 0, 16(t0)
- cache 0, 32(t0)
- cache 0, 48(t0)
- cache 0, 64(t0)
- cache 0, 80(t0)
- cache 0, 96(t0)
- cache 0, 112(t0)
+ cache C_IINV_I, 0(t0)
+ cache C_IINV_I, 16(t0)
+ cache C_IINV_I, 32(t0)
+ cache C_IINV_I, 48(t0)
+ cache C_IINV_I, 64(t0)
+ cache C_IINV_I, 80(t0)
+ cache C_IINV_I, 96(t0)
+ cache C_IINV_I, 112(t0)
bne t0, t1, 1b
addu t0, t0, 128
@@ -1491,14 +1515,14 @@
addu t1, t0, t2 # End address
subu t1, t1, 128
1:
- cache 1, 0(t0)
- cache 1, 16(t0)
- cache 1, 32(t0)
- cache 1, 48(t0)
- cache 1, 64(t0)
- cache 1, 80(t0)
- cache 1, 96(t0)
- cache 1, 112(t0)
+ cache C_IWBINV_D, 0(t0)
+ cache C_IWBINV_D, 16(t0)
+ cache C_IWBINV_D, 32(t0)
+ cache C_IWBINV_D, 48(t0)
+ cache C_IWBINV_D, 64(t0)
+ cache C_IWBINV_D, 80(t0)
+ cache C_IWBINV_D, 96(t0)
+ cache C_IWBINV_D, 112(t0)
bne t0, t1, 1b
addu t0, t0, 128
@@ -1509,10 +1533,10 @@
addu t1, t0, t2
subu t1, t1, 128
1:
- cache 3, 0(t0)
- cache 3, 32(t0)
- cache 3, 64(t0)
- cache 3, 96(t0)
+ cache C_IWBINV_SD, 0(t0)
+ cache C_IWBINV_SD, 32(t0)
+ cache C_IWBINV_SD, 64(t0)
+ cache C_IWBINV_SD, 96(t0)
bne t0, t1, 1b
addu t0, t0, 128
2:
@@ -1544,14 +1568,14 @@
addu a1, 127 # Align
srl a1, a1, 7 # Number of unrolled loops
1:
- cache 0, 0(a0)
- cache 0, 16(a0)
- cache 0, 32(a0)
- cache 0, 48(a0)
- cache 0, 64(a0)
- cache 0, 80(a0)
- cache 0, 96(a0)
- cache 0, 112(a0)
+ cache C_IINV_I, 0(a0)
+ cache C_IINV_I, 16(a0)
+ cache C_IINV_I, 32(a0)
+ cache C_IINV_I, 48(a0)
+ cache C_IINV_I, 64(a0)
+ cache C_IINV_I, 80(a0)
+ cache C_IINV_I, 96(a0)
+ cache C_IINV_I, 112(a0)
addu a1, -1
bne a1, zero, 1b
addu a0, 128
@@ -1593,14 +1617,14 @@
srl a1, a1, 7 # Compute number of cache lines
move t1, a1 # copy length
1:
- cache 1, 0(a0)
- cache 1, 16(a0)
- cache 1, 32(a0)
- cache 1, 48(a0)
- cache 1, 64(a0)
- cache 1, 80(a0)
- cache 1, 96(a0)
- cache 1, 112(a0)
+ cache C_IWBINV_D, 0(a0)
+ cache C_IWBINV_D, 16(a0)
+ cache C_IWBINV_D, 32(a0)
+ cache C_IWBINV_D, 48(a0)
+ cache C_IWBINV_D, 64(a0)
+ cache C_IWBINV_D, 80(a0)
+ cache C_IWBINV_D, 96(a0)
+ cache C_IWBINV_D, 112(a0)
addu a1, -1
bne a1, zero, 1b
addu a0, 128
@@ -1612,10 +1636,10 @@
li a0, MIPS_KSEG0_START
addu a0, a0, t0 # reduce to kseg0 address
1:
- cache 3, 0(a0)
- cache 3, 32(a0)
- cache 3, 64(a0)
- cache 3, 96(a0)
+ cache C_IWBINV_SD, 0(a0)
+ cache C_IWBINV_SD, 32(a0)
+ cache C_IWBINV_SD, 64(a0)
+ cache C_IWBINV_SD, 96(a0)
addu t1, -1
bne t1, zero, 1b
addu a0, 128
@@ -1654,19 +1678,19 @@
subu a1, a1, a0
srl a1, a1, 7 # Compute number of cache lines
1:
- cache 0x15, 0(a0)
- cache 0x15, 16(a0)
- cache 0x15, 32(a0)
- cache 0x15, 48(a0)
- cache 0x15, 64(a0)
- cache 0x15, 80(a0)
- cache 0x15, 96(a0)
- cache 0x15, 112(a0)
+ cache C_HWBINV_D, 0(a0)
+ cache C_HWBINV_D, 16(a0)
+ cache C_HWBINV_D, 32(a0)
+ cache C_HWBINV_D, 48(a0)
+ cache C_HWBINV_D, 64(a0)
+ cache C_HWBINV_D, 80(a0)
+ cache C_HWBINV_D, 96(a0)
+ cache C_HWBINV_D, 112(a0)
#if 1
- cache 0x17, 0(a0)
- cache 0x17, 32(a0)
- cache 0x17, 64(a0)
- cache 0x17, 96(a0)
+ cache C_HWBINV_SD, 0(a0)
+ cache C_HWBINV_SD, 32(a0)
+ cache C_HWBINV_SD, 64(a0)
+ cache C_HWBINV_SD, 96(a0)
#endif
addu a1, -1
bne a1, zero, 1b
@@ -1698,27 +1722,15 @@
LEAF(mips3_InvalidateDCache)
addu a1, a1, a0 # compute ending address
1:
- cache 0x13, 0(a0)
+ cache C_HINV_SD, 0(a0)
addu a0, a0, 4
bne a0, a1, 1b
- cache 0x11,-4(a0)
+ cache C_HINV_D,-4(a0)
j ra
nop
END(mips3_InvalidateDCache)
-/*
- * XXX mips/include
- */
-#define C_ICACHE 0
-#define C_DCACHE 1
-
-#define C_IINV (0 << 2)
-#define C_IWBINV (0 << 2)
-#define C_HINV (4 << 2)
-#define C_HWBINV (5 << 2)
-#define C_HWB (6 << 2)
-
/*----------------------------------------------------------------------------
*
* mips3_FlushCache_2way --
@@ -1745,15 +1757,15 @@
or t3, t1, t0 # Second way address
addu t1, t0, t1 # End address
1:
- cache C_ICACHE|C_IINV, 0(t0)
- cache C_ICACHE|C_IINV, 0(t3)
- cache C_ICACHE|C_IINV, 32(t0)
- cache C_ICACHE|C_IINV, 32(t3)
- cache C_ICACHE|C_IINV, 64(t0)
- cache C_ICACHE|C_IINV, 64(t3)
- cache C_ICACHE|C_IINV, 96(t0)
+ cache C_IINV_I, 0(t0)
+ cache C_IINV_I, 0(t3)
+ cache C_IINV_I, 32(t0)
+ cache C_IINV_I, 32(t3)
+ cache C_IINV_I, 64(t0)
+ cache C_IINV_I, 64(t3)
+ cache C_IINV_I, 96(t0)
addu t0, t0, 128
- cache C_ICACHE|C_IINV, 96(t3)
+ cache C_IINV_I, 96(t3)
bne t0, t1, 1b
addu t3, t3, 128 # Branch delay slot
@@ -1765,15 +1777,15 @@
or t3, t2, t0 # Second way address
addu t1, t0, t2 # End address
1:
- cache C_DCACHE|C_IWBINV, 0(t0)
- cache C_DCACHE|C_IWBINV, 0(t3)
- cache C_DCACHE|C_IWBINV, 32(t0)
- cache C_DCACHE|C_IWBINV, 32(t3)
- cache C_DCACHE|C_IWBINV, 64(t0)
- cache C_DCACHE|C_IWBINV, 64(t3)
- cache C_DCACHE|C_IWBINV, 96(t0)
+ cache C_IWBINV_D, 0(t0)
+ cache C_IWBINV_D, 0(t3)
+ cache C_IWBINV_D, 32(t0)
+ cache C_IWBINV_D, 32(t3)
+ cache C_IWBINV_D, 64(t0)
+ cache C_IWBINV_D, 64(t3)
+ cache C_IWBINV_D, 96(t0)
addu t0, t0, 128
- cache C_DCACHE|C_IWBINV, 96(t3)
+ cache C_IWBINV_D, 96(t3)
bne t0, t1, 1b
addu t3, t3, 128 # Branch delay slot
@@ -1785,10 +1797,10 @@
addu t1, t0, t2
subu t1, t1, 128
1:
- cache 3, 0(t0)
- cache 3, 32(t0)
- cache 3, 64(t0)
- cache 3, 96(t0)
+ cache C_IWBINV_SD, 0(t0)
+ cache C_IWBINV_SD, 32(t0)
+ cache C_IWBINV_SD, 64(t0)
+ cache C_IWBINV_SD, 96(t0)
bne t0, t1, 1b
addu t0, t0, 128
2:
@@ -1834,16 +1846,16 @@
srl a1, a1, 7 # Number of unrolled loops
or t0, t0, a0 # Way 1 index offset.
1:
- cache C_ICACHE|C_IINV, 0(a0)
- cache C_ICACHE|C_IINV, 0(t0) # other way
- cache C_ICACHE|C_IINV, 32(a0)
- cache C_ICACHE|C_IINV, 32(t0) # other way
+ cache C_IINV_I, 0(a0)
+ cache C_IINV_I, 0(t0) # other way
+ cache C_IINV_I, 32(a0)
+ cache C_IINV_I, 32(t0) # other way
addu a1, -1
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