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[src/trunk]: src/sys/arch/arc/arc Moved from /cvsroot/syssrc/sys/arch/pica/pi...
details: https://anonhg.NetBSD.org/src/rev/4f19512ace1b
branches: trunk
changeset: 481104:4f19512ace1b
user: soda <soda%NetBSD.org@localhost>
date: Sun Jan 23 20:09:10 2000 +0000
description:
Moved from /cvsroot/syssrc/sys/arch/pica/pica/locore.S,v
diffstat:
sys/arch/arc/arc/locore.S | 4178 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 4178 insertions(+), 0 deletions(-)
diffs (truncated from 4182 to 300 lines):
diff -r a70575c6c720 -r 4f19512ace1b sys/arch/arc/arc/locore.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arc/arc/locore.S Sun Jan 23 20:09:10 2000 +0000
@@ -0,0 +1,4178 @@
+/* $NetBSD: locore.S,v 1.9 2000/01/23 20:09:10 soda Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * @(#)locore.s 8.5 (Berkeley) 1/4/94
+ */
+
+/*
+ * Contains code that is the first executed at boot time plus
+ * assembly language support routines.
+ */
+
+#include <sys/errno.h>
+#include <sys/syscall.h>
+
+#include <machine/param.h>
+#include <machine/psl.h>
+#include <machine/asm.h>
+#include <machine/regnum.h>
+#include <machine/pte.h>
+
+#include "assym.h"
+
+ .set noreorder
+
+/*
+ * Amount to take off of the stack for the benefit of the debugger.
+ */
+#define START_FRAME ((4 * 4) + 4 + 4)
+
+ .globl start
+ .globl _C_LABEL(kernel_text)
+start:
+_C_LABEL(kernel_text):
+ mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
+ mtc0 zero, MIPS_COP_0_CAUSE_REG # Clear soft interrupts
+
+/*
+ * Initialize stack and call machine startup.
+ */
+ la sp, start - START_FRAME
+#ifdef __GP_SUPPORT__
+ la gp, _C_LABEL(_gp)
+#endif
+ sw zero, START_FRAME - 4(sp) # Zero out old ra for debugger
+ jal mips_init # mips_init(argc, argv, envp)
+ sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger
+
+ li t0, MIPS_SR_COP_1_BIT # Disable interrupts and
+ mtc0 t0, MIPS_COP_0_STATUS_REG # enable the fp coprocessor
+ li sp, KERNELSTACK - START_FRAME # switch to standard stack
+ mfc0 t0, MIPS_COP_0_PRID # read processor ID register
+
+ nop # XXX r4000 pipeline:
+ nop # wait for new status to
+ nop # to be effective
+ nop
+ cfc1 t1, MIPS_FPU_ID # read FPU ID register
+ sw t0, _C_LABEL(cpu_id) # save PRID register
+ sw t1, _C_LABEL(fpu_id) # save FPU ID register
+ jal _C_LABEL(main) # main(regs)
+ move a0, zero
+/*
+ * proc[1] == /etc/init now running here.
+ * Restore user registers and return.
+ */
+ .set noat
+ li v0, MIPS_SR_EXL
+ mtc0 v0, MIPS_COP_0_STATUS_REG # set exeption level bit.
+ lw a0, UADDR+U_PCB_REGS+(SR * 4)
+ lw t0, UADDR+U_PCB_REGS+(MULLO * 4)
+ lw t1, UADDR+U_PCB_REGS+(MULHI * 4)
+ mtlo t0
+ mthi t1
+ lw a0, UADDR+U_PCB_REGS+(PC * 4)
+ lw AT, UADDR+U_PCB_REGS+(AST * 4)
+ lw v0, UADDR+U_PCB_REGS+(V0 * 4)
+ dmtc0 a0, MIPS_COP_0_EXC_PC # set return address
+ li a0, PSL_USERSET
+ mtc0 a0, MIPS_COP_0_STATUS_REG # switch to user mode
+ lw v1, UADDR+U_PCB_REGS+(V1 * 4)
+ lw a0, UADDR+U_PCB_REGS+(A0 * 4)
+ lw a1, UADDR+U_PCB_REGS+(A1 * 4)
+ lw a2, UADDR+U_PCB_REGS+(A2 * 4)
+ lw a3, UADDR+U_PCB_REGS+(A3 * 4)
+ lw t0, UADDR+U_PCB_REGS+(T0 * 4)
+ lw t1, UADDR+U_PCB_REGS+(T1 * 4)
+ lw t2, UADDR+U_PCB_REGS+(T2 * 4)
+ lw t3, UADDR+U_PCB_REGS+(T3 * 4)
+ lw t4, UADDR+U_PCB_REGS+(T4 * 4)
+ lw t5, UADDR+U_PCB_REGS+(T5 * 4)
+ lw t6, UADDR+U_PCB_REGS+(T6 * 4)
+ lw t7, UADDR+U_PCB_REGS+(T7 * 4)
+ lw s0, UADDR+U_PCB_REGS+(S0 * 4)
+ lw s1, UADDR+U_PCB_REGS+(S1 * 4)
+ lw s2, UADDR+U_PCB_REGS+(S2 * 4)
+ lw s3, UADDR+U_PCB_REGS+(S3 * 4)
+ lw s4, UADDR+U_PCB_REGS+(S4 * 4)
+ lw s5, UADDR+U_PCB_REGS+(S5 * 4)
+ lw s6, UADDR+U_PCB_REGS+(S6 * 4)
+ lw s7, UADDR+U_PCB_REGS+(S7 * 4)
+ lw t8, UADDR+U_PCB_REGS+(T8 * 4)
+ lw t9, UADDR+U_PCB_REGS+(T9 * 4)
+ lw gp, UADDR+U_PCB_REGS+(GP * 4)
+ lw sp, UADDR+U_PCB_REGS+(SP * 4)
+ lw s8, UADDR+U_PCB_REGS+(S8 * 4)
+ lw ra, UADDR+U_PCB_REGS+(RA * 4)
+ eret
+ .set at
+
+/*
+ * GCC2 seems to want to call __main in main() for some reason.
+ */
+LEAF(__main)
+ j ra
+ nop
+END(__main)
+
+/*
+ * Primitives
+ */
+
+/*
+ * This table is indexed by u.u_pcb.pcb_onfault in trap().
+ * The reason for using this table rather than storing an address in
+ * u.u_pcb.pcb_onfault is simply to make the code faster.
+ */
+ .globl onfault_table
+ .data
+ .align 2
+_C_LABEL(onfault_table):
+ .word 0 # invalid index number
+#define BADERR 1
+ .word _C_LABEL(baderr)
+#define COPYERR 2
+ .word _C_LABEL(copyerr)
+#define FSWBERR 3
+ .word _C_LABEL(fswberr)
+#define FSWINTRBERR 4
+ .word _C_LABEL(fswintrberr)
+#ifdef DEBUG
+#define MDBERR 5
+ .word _C_LABEL(mdberr)
+#endif
+ .text
+
+/*
+ * See if access to addr with a len type instruction causes a machine check.
+ * len is length of access (1=byte, 2=short, 4=long)
+ *
+ * badaddr(addr, len)
+ * char *addr;
+ * int len;
+ */
+LEAF(badaddr)
+ li v0, BADERR
+ bne a1, 1, 2f
+ sw v0, UADDR+U_PCB_ONFAULT
+ b 5f
+ lbu v0, (a0)
+2:
+ bne a1, 2, 4f
+ nop
+ b 5f
+ lhu v0, (a0)
+4:
+ lw v0, (a0)
+5:
+ sw zero, UADDR+U_PCB_ONFAULT
+ j ra
+ move v0, zero # made it w/o errors
+baderr:
+ j ra
+ li v0, 1 # trap sends us here
+END(badaddr)
+
+/*
+ * This code is copied the user's stack for returning from signal handlers
+ * (see sendsig() and sigreturn()). We have to compute the address
+ * of the sigcontext struct for the sigreturn call.
+ */
+ .globl sigcode
+sigcode:
+ addu a0, sp, 16 # address of sigcontext
+ li v0, SYS_sigreturn # sigreturn(scp)
+ syscall
+ break 0 # just in case sigreturn fails
+ .globl esigcode
+esigcode:
+
+/*
+ * netorder = htonl(hostorder)
+ * hostorder = ntohl(netorder)
+ */
+LEAF(htonl) # a0 = 0x11223344, return 0x44332211
+ALEAF(ntohl)
+ srl v1, a0, 24 # v1 = 0x00000011
+ sll v0, a0, 24 # v0 = 0x44000000
+ or v0, v0, v1
+ and v1, a0, 0xff00
+ sll v1, v1, 8 # v1 = 0x00330000
+ or v0, v0, v1
+ srl v1, a0, 8
+ and v1, v1, 0xff00 # v1 = 0x00002200
+ j ra
+ or v0, v0, v1
+END(htonl)
+
+/*
+ * netorder = htons(hostorder)
+ * hostorder = ntohs(netorder)
+ */
+LEAF(htons)
+ALEAF(ntohs)
+ srl v0, a0, 8
+ and v0, v0, 0xff
+ sll v1, a0, 8
+ and v1, v1, 0xff00
+ j ra
+ or v0, v0, v1
+END(htons)
+
+/*
+ * bit = ffs(value)
+ */
+LEAF(ffs)
+ beq a0, zero, 2f
+ move v0, zero
+1:
+ and v1, a0, 1 # bit set?
+ addu v0, v0, 1
+ beq v1, zero, 1b # no, continue
+ srl a0, a0, 1
+2:
+ j ra
+ nop
+END(ffs)
+
+/*
+ * strlen(str)
+ */
+LEAF(strlen)
+ addu v1, a0, 1
+1:
+ lb v0, 0(a0) # get byte from string
+ addu a0, a0, 1 # increment pointer
+ bne v0, zero, 1b # continue if not end
+ nop
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