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[src/trunk]: src/sys/arch/mips Add support for the the Alchemy Semiconductor ...
details: https://anonhg.NetBSD.org/src/rev/aa16f7780b38
branches: trunk
changeset: 534561:aa16f7780b38
user: simonb <simonb%NetBSD.org@localhost>
date: Mon Jul 29 15:39:11 2002 +0000
description:
Add support for the the Alchemy Semiconductor Au1x00 series on-chip
devices. Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
diffstat:
sys/arch/mips/alchemy/au_cpureg_mem.c | 59 +
sys/arch/mips/alchemy/au_icu.c | 434 +++++++++++
sys/arch/mips/alchemy/au_timer.c | 146 ++++
sys/arch/mips/alchemy/aubus.c | 243 ++++++
sys/arch/mips/alchemy/dev/auaudio.c | 69 +
sys/arch/mips/alchemy/dev/aucom_aubus.c | 112 +++
sys/arch/mips/alchemy/dev/aurtc.c | 136 +++
sys/arch/mips/alchemy/dev/if_aumac.c | 1086 ++++++++++++++++++++++++++++++
sys/arch/mips/alchemy/dev/if_aumacreg.h | 176 ++++
sys/arch/mips/alchemy/dev/ohci.c | 73 ++
sys/arch/mips/alchemy/include/aubusvar.h | 25 +
sys/arch/mips/alchemy/include/aureg.h | 544 +++++++++++++++
sys/arch/mips/alchemy/include/auvar.h | 58 +
sys/arch/mips/conf/files.alchemy | 36 +
14 files changed, 3197 insertions(+), 0 deletions(-)
diffs (truncated from 3253 to 300 lines):
diff -r e0cf90760442 -r aa16f7780b38 sys/arch/mips/alchemy/au_cpureg_mem.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/au_cpureg_mem.c Mon Jul 29 15:39:11 2002 +0000
@@ -0,0 +1,59 @@
+/* $NetBSD: au_cpureg_mem.c,v 1.1 2002/07/29 15:39:11 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Platform-specific SOC register support for the Alchemy Semiconductor Au1X00.
+ */
+
+#include <sys/param.h>
+
+#include <machine/bus.h>
+#include <mips/alchemy/include/auvar.h>
+#include <mips/alchemy/include/aubusvar.h>
+
+#define CHIP au_cpureg
+#define CHIP_MEM /* defined */
+#define CHIP_ACCESSTYPE uint32_t
+
+/* MEM region 1 */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0x1fffffffUL
+#define CHIP_W1_SYS_START(v) 0UL
+#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
diff -r e0cf90760442 -r aa16f7780b38 sys/arch/mips/alchemy/au_icu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/au_icu.c Mon Jul 29 15:39:11 2002 +0000
@@ -0,0 +1,434 @@
+/* $NetBSD: au_icu.c,v 1.1 2002/07/29 15:39:11 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs.
+ *
+ * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal
+ * interrupt controllers.
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <mips/locore.h>
+#include <mips/alchemy/include/aureg.h>
+#include <mips/alchemy/include/auvar.h>
+
+#if 0
+#include <evbmips/evbmips/clockvar.h>
+#include <mips/alchemy/include/aubusvar.h>
+#endif
+
+#include <dev/ic/mc146818reg.h>
+
+#define REGVAL(x) *((__volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
+
+/*
+ * This is a mask of bits to clear in the SR when we go to a
+ * given hardware interrupt priority level.
+ */
+
+// #define ENABLE_AUMAC_HW1 /* XXX */
+#undef ENABLE_AUMAC_HW1 /* XXX */
+
+const u_int32_t ipl_sr_bits[_IPL_N] = {
+ 0, /* 0: IPL_NONE */
+
+ MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
+
+ MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTCLOCK */
+
+ MIPS_SOFT_INT_MASK_0, /* 3: IPL_SOFTNET */
+
+ MIPS_SOFT_INT_MASK_0, /* 4: IPL_SOFTSERIAL */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0, /* 5: IPL_BIO */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0, /* 6: IPL_NET */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0|
+#ifdef ENABLE_AUMAC_HW1
+ MIPS_INT_MASK_1, /* 7: IPL_AUMAC */
+#else
+ 0, /* 7: IPL_AUMAC */
+#endif
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0, /* 8: IPL_{SERIAL,TTY} */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0|
+#ifdef ENABLE_AUMAC_HW1
+ /* nothing */
+#else
+ MIPS_INT_MASK_1| /* XXX */
+#endif
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_3|
+ MIPS_INT_MASK_4|
+ MIPS_INT_MASK_5, /* 9: IPL_{CLOCK,HIGH} */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_0|
+ MIPS_INT_MASK_1|
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_3|
+ MIPS_INT_MASK_4|
+ MIPS_INT_MASK_5, /* 10: IPL_EXTREME */
+};
+
+/*
+ * This is a mask of bits to clear in the SR when we go to a
+ * given software interrupt priority level.
+ * Hardware ipls are port/board specific.
+ */
+const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFTNET */
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFTSERIAL */
+};
+
+#define NIRQS 64
+
+const char *au1000_intrnames[NIRQS] = {
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "ssi0",
+ "ssi1",
+ "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "pc0",
+ "pc0 match1",
+ "pc0 match2",
+ "pc0 match3",
+ "pc1",
+ "pc1 match1",
+ "pc1 match2",
+ "pc1 match3",
+ "irda tx",
+ "irda rx",
+ "usb intr",
+ "usb suspend",
+ "usb host",
+ "ac97",
+ "mac0",
+ "mac1",
+ "i2s",
+ "ac97 cmd",
+
+ "gpio 0",
+ "gpio 1",
+ "gpio 2",
+ "gpio 3",
+ "gpio 4",
+ "gpio 5",
+ "gpio 6",
+ "gpio 7",
+ "gpio 8",
+ "gpio 9",
+ "gpio 10",
+ "gpio 11",
+ "gpio 12",
+ "gpio 13",
+ "gpio 14",
+ "gpio 15",
+ "gpio 16",
+ "gpio 17",
+ "gpio 18",
+ "gpio 19",
+ "gpio 20",
+ "gpio 21",
+ "gpio 22",
+ "gpio 23",
+ "gpio 24",
+ "gpio 25",
+ "gpio 26",
+ "gpio 27",
+ "gpio 28",
+ "gpio 29",
+ "gpio 30",
+ "gpio 31",
+};
+
+struct au1000_intrhead {
+ struct evcnt intr_count;
+ int intr_refcnt;
+};
+struct au1000_intrhead au1000_intrtab[NIRQS];
+
+#define NINTRS 4 /* MIPS INT0 - INT3 */
+
+struct au1000_cpuintr {
+ LIST_HEAD(, evbmips_intrhand) cintr_list;
+ struct evcnt cintr_count;
+};
+
+struct au1000_cpuintr au1000_cpuintrs[NINTRS];
+const char *au1000_cpuintrnames[NINTRS] = {
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