Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/gnu/dist Snarf AltiVec goo from binutils-current.
details: https://anonhg.NetBSD.org/src/rev/ee2fa3f02080
branches: trunk
changeset: 515909:ee2fa3f02080
user: mycroft <mycroft%NetBSD.org@localhost>
date: Mon Oct 08 08:42:56 2001 +0000
description:
Snarf AltiVec goo from binutils-current.
diffstat:
gnu/dist/include/opcode/ppc.h | 15 +-
gnu/dist/opcodes/ppc-dis.c | 17 +-
gnu/dist/opcodes/ppc-opc.c | 1396 +++++++++++++++++++++++++++-------------
3 files changed, 951 insertions(+), 477 deletions(-)
diffs (truncated from 2202 to 300 lines):
diff -r 7a8c7a039f32 -r ee2fa3f02080 gnu/dist/include/opcode/ppc.h
--- a/gnu/dist/include/opcode/ppc.h Mon Oct 08 07:50:17 2001 +0000
+++ b/gnu/dist/include/opcode/ppc.h Mon Oct 08 08:42:56 2001 +0000
@@ -1,5 +1,5 @@
/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@@ -85,6 +85,12 @@
for the assembler's -many option, and it eliminates duplicates). */
#define PPC_OPCODE_ANY (0200)
+/* Opcode is supported as part of the 64-bit bridge. */
+#define PPC_OPCODE_64_BRIDGE (0400)
+
+/* Opcode is supported by Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC (01000)
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -218,6 +224,13 @@
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (04000)
+
+/* This operand names a vector unit register. The disassembler
+ prints these with a leading 'v'. */
+#define PPC_OPERAND_VR (010000)
+
+/* This operand is for the DS field in a DS form instruction. */
+#define PPC_OPERAND_DS (020000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
diff -r 7a8c7a039f32 -r ee2fa3f02080 gnu/dist/opcodes/ppc-dis.c
--- a/gnu/dist/opcodes/ppc-dis.c Mon Oct 08 07:50:17 2001 +0000
+++ b/gnu/dist/opcodes/ppc-dis.c Mon Oct 08 08:42:56 2001 +0000
@@ -1,5 +1,5 @@
/* ppc-dis.c -- Disassemble PowerPC instructions
- Copyright 1994 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@@ -19,7 +19,6 @@
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
-#include "ansidecl.h"
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/ppc.h"
@@ -34,7 +33,8 @@
int bigendian, int dialect));
/* Print a big endian PowerPC instruction. For convenience, also
- disassemble instructions supported by the Motorola PowerPC 601. */
+ disassemble instructions supported by the Motorola PowerPC 601
+ and the Altivec vector unit. */
int
print_insn_big_powerpc (memaddr, info)
@@ -42,11 +42,13 @@
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 1,
- PPC_OPCODE_PPC | PPC_OPCODE_601);
+ PPC_OPCODE_PPC | PPC_OPCODE_601 |
+ PPC_OPCODE_ALTIVEC);
}
/* Print a little endian PowerPC instruction. For convenience, also
- disassemble instructions supported by the Motorola PowerPC 601. */
+ disassemble instructions supported by the Motorola PowerPC 601
+ and the Altivec vector unit. */
int
print_insn_little_powerpc (memaddr, info)
@@ -54,7 +56,8 @@
struct disassemble_info *info;
{
return print_insn_powerpc (memaddr, info, 0,
- PPC_OPCODE_PPC | PPC_OPCODE_601);
+ PPC_OPCODE_PPC | PPC_OPCODE_601 |
+ PPC_OPCODE_ALTIVEC);
}
/* Print a POWER (RS/6000) instruction. */
@@ -182,6 +185,8 @@
(*info->fprintf_func) (info->stream, "r%ld", value);
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
(*info->fprintf_func) (info->stream, "f%ld", value);
+ else if ((operand->flags & PPC_OPERAND_VR) != 0)
+ (*info->fprintf_func) (info->stream, "v%ld", value);
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
(*info->print_address_func) (memaddr + value, info);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
diff -r 7a8c7a039f32 -r ee2fa3f02080 gnu/dist/opcodes/ppc-opc.c
--- a/gnu/dist/opcodes/ppc-opc.c Mon Oct 08 07:50:17 2001 +0000
+++ b/gnu/dist/opcodes/ppc-opc.c Mon Oct 08 08:42:56 2001 +0000
@@ -1,5 +1,6 @@
/* ppc-opc.c -- PowerPC opcode list
- Copyright 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
+ Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@@ -20,7 +21,7 @@
02111-1307, USA. */
#include <stdio.h>
-#include "ansidecl.h"
+#include "sysdep.h"
#include "opcode/ppc.h"
/* This file holds the PowerPC opcode table. The opcode table
@@ -77,7 +78,14 @@
/* The operands table.
- The fields are bits, shift, insert, extract, flags. */
+ The fields are bits, shift, insert, extract, flags.
+
+ We used to put parens around the various additions, like the one
+ for BA just below. However, that caused trouble with feeble
+ compilers with a limit on depth of a parenthesized expression, like
+ (reportedly) the compiler in Microsoft Developer Studio 5. So we
+ omit the parens, since the macros are never used in a context where
+ the addition will be ambiguous. */
const struct powerpc_operand powerpc_operands[] =
{
@@ -87,177 +95,182 @@
{ 0, 0, 0, 0, 0 },
/* The BA field in an XL form instruction. */
-#define BA (UNUSED + 1)
+#define BA UNUSED + 1
#define BA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */
-#define BAT (BA + 1)
+#define BAT BA + 1
{ 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
/* The BB field in an XL form instruction. */
-#define BB (BAT + 1)
+#define BB BAT + 1
#define BB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_CR },
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
-#define BBA (BB + 1)
+#define BBA BB + 1
{ 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
/* The BD field in a B form instruction. The lower two bits are
forced to zero. */
-#define BD (BBA + 1)
+#define BD BBA + 1
{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when absolute addressing is
used. */
-#define BDA (BD + 1)
+#define BDA BD + 1
{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used.
This sets the y bit of the BO field appropriately. */
-#define BDM (BDA + 1)
+#define BDM BDA + 1
{ 16, 0, insert_bdm, extract_bdm,
PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used
and absolute address is used. */
-#define BDMA (BDM + 1)
+#define BDMA BDM + 1
{ 16, 0, insert_bdm, extract_bdm,
PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used.
This sets the y bit of the BO field appropriately. */
-#define BDP (BDMA + 1)
+#define BDP BDMA + 1
{ 16, 0, insert_bdp, extract_bdp,
PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used
and absolute addressing is used. */
-#define BDPA (BDP + 1)
+#define BDPA BDP + 1
{ 16, 0, insert_bdp, extract_bdp,
PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BF field in an X or XL form instruction. */
-#define BF (BDPA + 1)
+#define BF BDPA + 1
{ 3, 23, 0, 0, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
-#define OBF (BF + 1)
+#define OBF BF + 1
{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
-#define BFA (OBF + 1)
+#define BFA OBF + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR },
/* The BI field in a B form or XL form instruction. */
-#define BI (BFA + 1)
+#define BI BFA + 1
#define BI_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BO field in a B form instruction. Certain values are
illegal. */
-#define BO (BI + 1)
+#define BO BI + 1
#define BO_MASK (0x1f << 21)
{ 5, 21, insert_bo, extract_bo, 0 },
/* The BO field in a B form instruction when the + or - modifier is
used. This is like the BO field, but it must be even. */
-#define BOE (BO + 1)
+#define BOE BO + 1
{ 5, 21, insert_boe, extract_boe, 0 },
/* The BT field in an X or XL form instruction. */
-#define BT (BOE + 1)
+#define BT BOE + 1
{ 5, 21, 0, 0, PPC_OPERAND_CR },
/* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */
-#define CR (BT + 1)
+#define CR BT + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
-#define D (CR + 1)
+#define D CR + 1
{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
-#define DS (D + 1)
- { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+#define DS D + 1
+ { 16, 0, insert_ds, extract_ds,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
-#define E (DS + 1)
+#define E DS + 1
{ 1, 15, 0, 0, 0 },
/* The FL1 field in a POWER SC form instruction. */
-#define FL1 (E + 1)
+#define FL1 E + 1
{ 4, 12, 0, 0, 0 },
/* The FL2 field in a POWER SC form instruction. */
-#define FL2 (FL1 + 1)
+#define FL2 FL1 + 1
{ 3, 2, 0, 0, 0 },
/* The FLM field in an XFL form instruction. */
-#define FLM (FL2 + 1)
+#define FLM FL2 + 1
{ 8, 17, 0, 0, 0 },
/* The FRA field in an X or A form instruction. */
-#define FRA (FLM + 1)
+#define FRA FLM + 1
#define FRA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_FPR },
/* The FRB field in an X or A form instruction. */
-#define FRB (FRA + 1)
+#define FRB FRA + 1
#define FRB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_FPR },
/* The FRC field in an A form instruction. */
-#define FRC (FRB + 1)
Home |
Main Index |
Thread Index |
Old Index