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[src/trunk]: src/sys/arch/mips R5900 support.
details: https://anonhg.NetBSD.org/src/rev/5e8bcf842788
branches: trunk
changeset: 516123:5e8bcf842788
user: uch <uch%NetBSD.org@localhost>
date: Tue Oct 16 16:31:32 2001 +0000
description:
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
diffstat:
sys/arch/mips/conf/Makefile.mips | 14 +-
sys/arch/mips/include/cpu.h | 12 +-
sys/arch/mips/include/cpuregs.h | 8 +-
sys/arch/mips/include/locore.h | 4 +-
sys/arch/mips/include/pcb.h | 3 +-
sys/arch/mips/include/proc.h | 4 +-
sys/arch/mips/include/r5900/cpuregs.h | 90 +++++++++++
sys/arch/mips/include/r5900/locore.h | 48 +++++
sys/arch/mips/mips/fpemu.c | 72 ++++++++-
sys/arch/mips/mips/genassym.cf | 5 +-
sys/arch/mips/mips/locore.S | 74 +++++++-
sys/arch/mips/mips/locore_mips3.S | 250 ++++++++++++++++++++++++++++++-
sys/arch/mips/mips/mips_machdep.c | 35 +++-
sys/arch/mips/mips/r5900/locore_r5900.S | 236 +++++++++++++++++++++++++++++
sys/arch/mips/mips/r5900/r5900_machdep.c | 117 ++++++++++++++
sys/arch/mips/mips/trap.c | 18 +-
sys/arch/mips/mips/vm_machdep.c | 7 +-
17 files changed, 956 insertions(+), 41 deletions(-)
diffs (truncated from 2329 to 300 lines):
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/conf/Makefile.mips
--- a/sys/arch/mips/conf/Makefile.mips Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/conf/Makefile.mips Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.mips,v 1.19 2001/10/08 10:14:20 simonb Exp $
+# $NetBSD: Makefile.mips,v 1.20 2001/10/16 16:31:32 uch Exp $
# Makefile for NetBSD
#
@@ -115,6 +115,9 @@
.if !empty(IDENT:M-DMIPS3)
SYSTEM_OBJ+= locore_mips3.o
.endif
+.if !empty(IDENT:M-DMIPS3_5900)
+SYSTEM_OBJ+= locore_r5900.o r5900_machdep.o
+.endif
.if empty(IDENT:M-DNOFPU)
SYSTEM_OBJ+= fp.o
.endif
@@ -202,6 +205,9 @@
.if !empty(IDENT:M-DMIPS3)
SFILES+=${MIPS}/mips/locore_mips3.S
.endif
+.if !empty(IDENT:M-DMIPS3_5900)
+SRCS+= ${MIPS}/mips/r5900/locore_r5900.S ${MIPS}/mips/r5900/r5900_machdep.c
+.endif
.if empty(IDENT:M-DNOFPU)
SFILES+=${MIPS}/mips/fp.S
.endif
@@ -245,6 +251,12 @@
locore_mips3.o: ${MIPS}/mips/locore_mips3.S assym.h
${NORMAL_S}
+locore_r5900.o: ${MIPS}/mips/r5900/locore_r5900.S assym.h
+ ${NORMAL_S}
+
+r5900_machdep.o: ${MIPS}/mips/r5900/r5900_machdep.c
+ ${NORMAL_C}
+
.if empty(IDENT:M-DNOFPU)
fp.o: ${MIPS}/mips/fp.S assym.h
${NORMAL_S}
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/cpu.h
--- a/sys/arch/mips/include/cpu.h Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/include/cpu.h Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.55 2001/09/04 09:23:27 simonb Exp $ */
+/* $NetBSD: cpu.h,v 1.56 2001/10/16 16:31:33 uch Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -138,6 +138,7 @@
struct clockframe {
int pc; /* program counter at time of interrupt */
int sr; /* status register at time of interrupt */
+ int ppl; /* previous priority level at time of interrupt */
};
/*
@@ -157,6 +158,10 @@
#define MIPS3_CLKF_BASEPRI(framep) \
((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0)
+#ifdef IPL_ICU_MASK
+#define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0)
+#endif
+
#define CLKF_PC(framep) ((framep)->pc)
#define CLKF_INTR(framep) (0)
@@ -170,6 +175,11 @@
#define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep)
#endif
+#ifdef IPL_ICU_MASK
+#undef CLKF_BASEPRI
+#define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep)
+#endif
+
#if defined(MIPS3) && defined(MIPS1)
#define CLKF_USERMODE(framep) \
((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep))
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/include/cpuregs.h Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.46 2001/08/17 07:53:33 simonb Exp $ */
+/* $NetBSD: cpuregs.h,v 1.47 2001/10/16 16:31:34 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -92,6 +92,8 @@
#define MIPS3_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
+/* CPU dependent mtc0 hazard hook */
+#define COP0_SYNC /* nothing */
/*
* The bits in the cause register.
@@ -670,6 +672,7 @@
#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
+#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
@@ -706,5 +709,8 @@
#ifdef ENABLE_MIPS_TX3900
#include <mips/r3900regs.h>
#endif
+#ifdef MIPS3_5900
+#include <mips/r5900/cpuregs.h>
+#endif
#endif /* _MIPS_CPUREGS_H_ */
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/include/locore.h Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.56 2001/08/18 04:13:28 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.57 2001/10/16 16:31:34 uch Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -235,6 +235,8 @@
mips_reg_t tf_mullo;
mips_reg_t tf_mulhi;
mips_reg_t tf_epc; /* may be changed by trap() call */
+ u_int32_t tf_ppl; /* previous priority level */
+ int32_t tf_pad; /* for 8 byte aligned */
};
/*
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/pcb.h
--- a/sys/arch/mips/include/pcb.h Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/include/pcb.h Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcb.h,v 1.11 2000/09/13 01:53:00 nisimura Exp $ */
+/* $NetBSD: pcb.h,v 1.12 2001/10/16 16:31:34 uch Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -52,6 +52,7 @@
struct fpreg pcb_fpregs; /* saved floating point registers */
mips_reg_t pcb_context[12]; /* kernel context for resume */
caddr_t pcb_onfault; /* for copyin/copyout faults */
+ u_int32_t pcb_ppl; /* previous priority level */
};
/*
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/proc.h
--- a/sys/arch/mips/include/proc.h Tue Oct 16 16:08:55 2001 +0000
+++ b/sys/arch/mips/include/proc.h Tue Oct 16 16:31:32 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.12 2001/01/16 06:01:26 thorpej Exp $ */
+/* $NetBSD: proc.h,v 1.13 2001/10/16 16:31:34 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -65,6 +65,8 @@
*/
struct frame {
mips_reg_t f_regs[38];
+ u_int32_t f_ppl; /* previous priority level */
+ int32_t f_pad; /* for 8 byte aligned */
};
#ifdef _KERNEL
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/r5900/cpuregs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/include/r5900/cpuregs.h Tue Oct 16 16:31:32 2001 +0000
@@ -0,0 +1,90 @@
+/* $NetBSD: cpuregs.h,v 1.1 2001/10/16 16:31:35 uch Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by UCHIYAMA Yasushi.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* R5900 has Enable Interrupt Enable bit. */
+#undef MIPS_SR_INT_IE
+#define MIPS_SR_INT_IE 0x00010001 /* EIE + IE */
+
+#undef COP0_SYNC
+#define COP0_SYNC sync.p
+
+/*
+ * R5900 has INT5,1,0 only don't support software interrupt
+ * MIPS_SOFT_INT_MASK_1 and MIPS_SOFT_INT_MASK_1 are emulated by kernel.
+ */
+#undef MIPS_INT_MASK
+#define MIPS_INT_MASK 0x0c00
+#undef MIPS_HARD_INT_MASK
+#define MIPS_HARD_INT_MASK 0x0c00
+
+#undef MIPS_COP_0_LLADDR
+#undef MIPS_COP_0_WATCH_LO
+#undef MIPS_COP_0_WATCH_HI
+#undef MIPS_COP_0_TLB_XCONTEXT
+#undef MIPS_COP_0_ECC
+#undef MIPS_COP_0_CACHE_ERR
+#undef MIPS_COP_0_DESAVE
+
+/* Exception vector */
+#define R5900_TLB_REFIL_EXC_VEC 0x80000000
+#define R5900_COUNTER_EXC_VEC 0x80000080
+#define R5900_DEBUG_EXC_VEC 0x80000100
+#define R5900_COMMON_EXC_VEC 0x80000180
+#define R5900_INTERRUPT_EXC_VEC 0x80000200
+
+/* Cache */
+#define R5900_C_SIZE_I 16384
+#define R5900_C_SIZE_D 8192
+
+#define R5900_C_LSIZE_I 64
+#define R5900_C_LSIZE_D 64
+
+#define R5900_C_IINV_I 0x07 /* INDEX INVALIDATE */
+#define R5900_C_IWBINV_D 0x14 /* INDEX WRITE BACK INVALIDATE */
+#define R5900_C_ILTG_D 0x10 /* INDEX LOAD TAG */
+#define R5900_C_ISTG_D 0x12 /* INDEX STORE TAG */
+#define R5900_C_IINV_D 0x16 /* INDEX INVALIDATE */
+#define R5900_C_HINV_D 0x1a /* HIT INVALIDATE */
+#define R5900_C_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */
+#define R5900_C_ILDT_D 0x11 /* INDEX LOAD DATA */
+#define R5900_C_ISDT_D 0x13 /* INDEX STORE DATA */
+#define R5900_C_HWBWOINV_D 0x1c /* HIT WRITEBACK W/O INVALIDATE */
+
+/* MMU R5900 support 32bit-mode only */
+#define dmtc0 mtc0
+#define dmfc0 mfc0
diff -r caa20bcc3f9b -r 5e8bcf842788 sys/arch/mips/include/r5900/locore.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/include/r5900/locore.h Tue Oct 16 16:31:32 2001 +0000
@@ -0,0 +1,48 @@
+/* $NetBSD: locore.h,v 1.1 2001/10/16 16:31:35 uch Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by UCHIYAMA Yasushi.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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