Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/arch/hpcarm/sa11x0 Map DMA controller and disable its DM...



details:   https://anonhg.NetBSD.org/src/rev/c743268fc597
branches:  trunk
changeset: 507410:c743268fc597
user:      toshii <toshii%NetBSD.org@localhost>
date:      Wed Mar 21 17:42:37 2001 +0000

description:
Map DMA controller and disable its DMA channels.

diffstat:

 sys/arch/hpcarm/sa11x0/sa11x0.c     |  16 +++++++++++++++-
 sys/arch/hpcarm/sa11x0/sa11x0_var.h |   3 ++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diffs (61 lines):

diff -r 239b8ffcb5e0 -r c743268fc597 sys/arch/hpcarm/sa11x0/sa11x0.c
--- a/sys/arch/hpcarm/sa11x0/sa11x0.c   Wed Mar 21 17:37:11 2001 +0000
+++ b/sys/arch/hpcarm/sa11x0/sa11x0.c   Wed Mar 21 17:42:37 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: sa11x0.c,v 1.6 2001/03/10 15:34:38 toshii Exp $        */
+/*     $NetBSD: sa11x0.c,v 1.7 2001/03/21 17:42:37 toshii Exp $        */
 
 /*-
  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
@@ -67,6 +67,7 @@
 #include <arm/mainbus/mainbus.h>
 #include <hpcarm/sa11x0/sa11x0_reg.h>
 #include <hpcarm/sa11x0/sa11x0_var.h>
+#include <hpcarm/sa11x0/sa11x0_dmacreg.h>
 #include <hpcarm/sa11x0/sa11x0_gpioreg.h>
 
 #include "locators.h"
@@ -162,6 +163,11 @@
                          0, &sc->sc_gpioh))
                panic("%s: unable to map GPIO registers\n", self->dv_xname);
 
+       /* Map the DMA controller registers */
+       if (bus_space_map(sc->sc_iot, SADMAC_BASE, SADMAC_NPORTS,
+                         0, &sc->sc_dmach))
+               panic("%s: unable to map DMAC registers\n", self->dv_xname);
+
        printf("\n");
 
        /*
@@ -176,6 +182,14 @@
        /* Clear idle mask */
        bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_CR, 0);
 
+       /* diable all DMAC channels */
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR0_CLR, 1);
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR1_CLR, 1);
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR2_CLR, 1);
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR3_CLR, 1);
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR4_CLR, 1);
+       bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR5_CLR, 1);
+
 #ifdef DEBUG  /* XXX */
        sa11x0_intr_establish(0, 30, 1, IPL_HIGH, hoge, 0);
        *((u_int32_t *)0xd0001010) = 0x8;
diff -r 239b8ffcb5e0 -r c743268fc597 sys/arch/hpcarm/sa11x0/sa11x0_var.h
--- a/sys/arch/hpcarm/sa11x0/sa11x0_var.h       Wed Mar 21 17:37:11 2001 +0000
+++ b/sys/arch/hpcarm/sa11x0/sa11x0_var.h       Wed Mar 21 17:42:37 2001 +0000
@@ -1,4 +1,4 @@
-/*      $NetBSD: sa11x0_var.h,v 1.3 2001/03/10 15:34:38 toshii Exp $        */
+/*      $NetBSD: sa11x0_var.h,v 1.4 2001/03/21 17:42:37 toshii Exp $        */
 
 /*-
  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
@@ -46,6 +46,7 @@
        bus_space_tag_t sc_iot;
        bus_space_handle_t sc_ioh;
        bus_space_handle_t sc_gpioh;
+       bus_space_handle_t sc_dmach;
        int sc_pri; /* attaching device priority */
        u_int32_t sc_intrmask;
 };



Home | Main Index | Thread Index | Old Index