[src/trunk]: src/sys/dev/ic Add some new features:

[bouyer <bouyer%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/37e4cc3d6c62
branches:  trunk
changeset: 526008:37e4cc3d6c62
user:      bouyer <bouyer%NetBSD.org@localhost>
date:      Tue Apr 23 10:06:44 2002 +0000

description:
Add some new features:
- SF_BUS_ULTRA3, for Ultra/3 (80Mhz) busses
- SF_CHIP_LEDC,  led on GPIO0 with hardware control
- SF_CHIP_DT, support DT clocking.

diffstat:

 sys/dev/ic/siopvar_common.h |  23 +++++++++++++----------
 1 files changed, 13 insertions(+), 10 deletions(-)

diffs (39 lines):

diff -r 64d4660124a9 -r 37e4cc3d6c62 sys/dev/ic/siopvar_common.h
--- a/sys/dev/ic/siopvar_common.h       Tue Apr 23 09:46:51 2002 +0000
+++ b/sys/dev/ic/siopvar_common.h       Tue Apr 23 10:06:44 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: siopvar_common.h,v 1.14 2002/04/20 15:25:53 bouyer Exp $       */
+/*     $NetBSD: siopvar_common.h,v 1.15 2002/04/23 10:06:44 bouyer Exp $       */
 
 /*
  * Copyright (c) 2000 Manuel Bouyer.
@@ -147,17 +147,20 @@
 #define SF_BUS_WIDE    0x00000001 /* wide bus */
 #define SF_BUS_ULTRA   0x00000002 /* Ultra (20Mhz) bus */
 #define SF_BUS_ULTRA2  0x00000004 /* Ultra2 (40Mhz) bus */
-#define SF_BUS_DIFF    0x00000008 /* differential bus */
+#define SF_BUS_ULTRA3  0x00000008 /* Ultra3 (80Mhz) bus */
+#define SF_BUS_DIFF    0x00000010 /* differential bus */
 
 #define SF_CHIP_LED0   0x00000100 /* led on GPIO0 */
-#define SF_CHIP_DBLR   0x00000200 /* clock doubler or quadrupler */
-#define SF_CHIP_QUAD   0x00000400 /* clock quadrupler, with PPL */
-#define SF_CHIP_FIFO   0x00000800 /* large fifo */
-#define SF_CHIP_PF     0x00001000 /* Intructions prefetch */
-#define SF_CHIP_RAM    0x00002000 /* on-board RAM */
-#define SF_CHIP_LS     0x00004000 /* load/store instruction */
-#define SF_CHIP_10REGS 0x00008000 /* 10 scratch registers */
-#define SF_CHIP_DFBC   0x00010000 /* Use DFBC register */
+#define SF_CHIP_LEDC   0x00000200 /* led on GPIO0 with hardware control */
+#define SF_CHIP_DBLR   0x00000400 /* clock doubler or quadrupler */
+#define SF_CHIP_QUAD   0x00000800 /* clock quadrupler, with PPL */
+#define SF_CHIP_FIFO   0x00001000 /* large fifo */
+#define SF_CHIP_PF     0x00002000 /* Intructions prefetch */
+#define SF_CHIP_RAM    0x00004000 /* on-board RAM */
+#define SF_CHIP_LS     0x00008000 /* load/store instruction */
+#define SF_CHIP_10REGS 0x00010000 /* 10 scratch registers */
+#define SF_CHIP_DFBC   0x00020000 /* Use DFBC register */
+#define SF_CHIP_DT     0x00040000 /* DT clocking */
 
 #define SF_PCI_RL      0x01000000 /* PCI read line */
 #define SF_PCI_RM      0x02000000 /* PCI read multiple */