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[src/trunk]: src/sys/arch/hpcarm/sa11x0 Instead of scheduling all interrupts ...
details: https://anonhg.NetBSD.org/src/rev/2fcc1ce7eb79
branches: trunk
changeset: 510210:2fcc1ce7eb79
user: toshii <toshii%NetBSD.org@localhost>
date: Tue May 22 17:54:50 2001 +0000
description:
Instead of scheduling all interrupts at IPL_BIO, use an IPL_SERIAL
handler to clear hardware interrupt bit and schedule actual handlers
using soft interrupts registered with desired IPL.
XXX This slows down interrupt handling a bit (up to a few percent with
XXX ping -f or make-over-NFS benchmarks) in some cases.
diffstat:
sys/arch/hpcarm/sa11x0/sa1111.c | 90 +++++++++++++-----------------------
sys/arch/hpcarm/sa11x0/sa1111_var.h | 12 +---
2 files changed, 37 insertions(+), 65 deletions(-)
diffs (239 lines):
diff -r 9711094cbea1 -r 2fcc1ce7eb79 sys/arch/hpcarm/sa11x0/sa1111.c
--- a/sys/arch/hpcarm/sa11x0/sa1111.c Tue May 22 17:50:05 2001 +0000
+++ b/sys/arch/hpcarm/sa11x0/sa1111.c Tue May 22 17:54:50 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sa1111.c,v 1.5 2001/05/19 05:07:02 toshii Exp $ */
+/* $NetBSD: sa1111.c,v 1.6 2001/05/22 17:54:50 toshii Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -38,7 +38,6 @@
/*
* TODO:
- * - implement IPL in intr handler
* - separate machine specific attach code
* - introduce bus abstraction to support SA1101
*/
@@ -67,10 +66,9 @@
static int sa1111_search(struct device *, struct cfdata *, void *);
static int sa1111_print(void *, const char *);
-static int sacc_intr_dispatch(void *);
-static void sacc_stray_interrupt(struct sacc_softc *, int);
static void sacc_intr_calculatemasks(struct sacc_softc *);
static void sacc_intr_setpolarity(sacc_chipset_tag_t *, int , int);
+int sacc_intr(void *);
struct platid_data sacc_platid_table[] = {
{ &platid_mask_MACH_HP_JORNADA_720, (void *)1 },
@@ -137,12 +135,7 @@
SACCIC_INTSTATCLR1, 0xffffffff);
/* connect to SA1110's GPIO intr */
-#ifdef notyet
- sa11x0_cascadeintr_establish(0, gpiopin, sacc_intr_probe,
- sacc_intr_mask, sc);
-#endif
- sa11x0_intr_establish(0, gpiopin,
- 1, IPL_BIO, sacc_intr_dispatch, sc);
+ sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc);
/*
* Attach each devices
@@ -171,11 +164,11 @@
return (UNCONF);
}
-static int
-sacc_intr_dispatch(arg)
+int
+sacc_intr(arg)
void *arg;
{
- int i, handled;
+ int i;
u_int32_t mask;
struct sacc_intrvec intstat;
struct sacc_softc *sc = arg;
@@ -187,11 +180,6 @@
bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1);
DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi));
- /* process the intrs which have the highest IPL */
-#ifdef notyet
- intstat.lo &= sc->sc_imask[xx].lo;
- intstat.hi &= sc->sc_imask[xx].hi;
-#endif
for(i = 0, mask = 1; i < 32; i++, mask <<= 1)
if (intstat.lo & mask) {
/* clear SA1110's GPIO intr status */
@@ -205,13 +193,8 @@
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
SACCIC_INTSTATCLR0, 1 << i);
- handled = 0;
for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
- handled = handled |
- ((ih->ih_fun)(ih->ih_arg) == 1);
-
- if (! handled)
- sacc_stray_interrupt(sc, i + 32);
+ softintr_schedule(ih->ih_soft);
}
for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1)
if (intstat.hi & mask) {
@@ -221,25 +204,12 @@
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
SACCIC_INTSTATCLR1, 1 << i);
- handled = 0;
for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
- handled = handled |
- ((ih->ih_fun)(ih->ih_arg) == 1);
-
- if (! handled)
- sacc_stray_interrupt(sc, i + 32);
+ softintr_schedule(ih->ih_soft);
}
return 1;
}
-static void
-sacc_stray_interrupt(sc, irq)
- struct sacc_softc *sc;
- int irq;
-{
- DPRINTF(("sacc_stray_interrupt\n"));
-}
-
void *
sacc_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
sacc_chipset_tag_t *ic;
@@ -260,22 +230,22 @@
! (type == IST_EDGE_RAISE || type == IST_EDGE_FALL))
panic("sacc_intr_establish: bogus irq or type");
+ if (sc->sc_intrhand[irq] == NULL) {
+ sacc_intr_setpolarity(ic, irq, type);
+ sc->sc_intrtype[irq] = type;
+ } else if (sc->sc_intrtype[irq] != type)
+ /* XXX we should be able to share raising and
+ * falling edge intrs */
+ panic("sacc_intr_establish: type must be unique\n");
+
/* install intr handler */
- ih->ih_fun = ih_fun;
- ih->ih_arg = ih_arg;
+ ih->ih_soft = softintr_establish(level, ih_fun, ih_arg);
ih->ih_irq = irq;
- ih->ih_type = type;
ih->ih_next = NULL;
s = splhigh();
for(p = &sc->sc_intrhand[irq]; *p; p = &(*p)->ih_next)
- if ((*p)->ih_type != type)
- /* XXX we should be able to share raising and
- * falling edge intrs */
- panic("sacc_intr_establish: type must be unique\n");
-
- if (sc->sc_intrhand[irq] == NULL)
- sacc_intr_setpolarity(ic, irq, type);
+ ;
*p = ih;
@@ -290,7 +260,7 @@
sacc_chipset_tag_t *ic;
void *arg;
{
- int irq;
+ int irq, s;
struct sacc_softc *sc = (struct sacc_softc *)ic;
struct sacc_intrhand *ih, **p;
@@ -302,6 +272,8 @@
panic("sacc_intr_disestablish: bogus irq");
#endif
+ s = splhigh();
+
for(p = &sc->sc_intrhand[irq];; p = &(*p)->ih_next) {
if (*p == NULL)
panic("sacc_intr_disestablish: handler not registered");
@@ -309,6 +281,10 @@
break;
}
*p = (*p)->ih_next;
+
+ sacc_intr_calculatemasks(sc);
+ splx(s);
+
free(ih, M_DEVBUF);
}
@@ -347,21 +323,21 @@
{
int irq;
- sc->sc_imask[0].lo = 0;
- sc->sc_imask[0].hi = 0;
+ sc->sc_imask.lo = 0;
+ sc->sc_imask.hi = 0;
for(irq = 0; irq < 32; irq++)
if (sc->sc_intrhand[irq])
- sc->sc_imask[0].lo |= (1 << irq);
+ sc->sc_imask.lo |= (1 << irq);
for(irq = 0; irq < SACCIC_LEN - 32; irq++)
if (sc->sc_intrhand[irq + 32])
- sc->sc_imask[0].hi |= (1 << irq);
+ sc->sc_imask.hi |= (1 << irq);
/* XXX this should not be done here */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0,
- sc->sc_imask[0].lo);
+ sc->sc_imask.lo);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1,
- sc->sc_imask[0].hi);
- DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask[0].lo,
- sc->sc_imask[0].hi));
+ sc->sc_imask.hi);
+ DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask.lo,
+ sc->sc_imask.hi));
}
diff -r 9711094cbea1 -r 2fcc1ce7eb79 sys/arch/hpcarm/sa11x0/sa1111_var.h
--- a/sys/arch/hpcarm/sa11x0/sa1111_var.h Tue May 22 17:50:05 2001 +0000
+++ b/sys/arch/hpcarm/sa11x0/sa1111_var.h Tue May 22 17:54:50 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sa1111_var.h,v 1.2 2001/03/21 16:08:34 toshii Exp $ */
+/* $NetBSD: sa1111_var.h,v 1.3 2001/05/22 17:54:50 toshii Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -37,13 +37,8 @@
*/
struct sacc_intrhand {
- int (*ih_fun)(void *);
- void *ih_arg;
+ void *ih_soft;
int ih_irq;
-#ifdef notyet
- int ih_level;
-#endif
- int ih_type;
struct sacc_intrhand *ih_next;
};
@@ -61,8 +56,9 @@
u_int32_t sc_gpiomask; /* SA1110 GPIO mask */
- struct sacc_intrvec sc_imask[NIPL];
+ struct sacc_intrvec sc_imask;
struct sacc_intrhand *sc_intrhand[SACCIC_LEN];
+ int sc_intrtype[SACCIC_LEN];
};
typedef void *sacc_chipset_tag_t;
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