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[src/trunk]: src/sys/arch/powerpc/powerpc resync the MP and non-MP trap_subr's.
details: https://anonhg.NetBSD.org/src/rev/d46b26b74227
branches: trunk
changeset: 534492:d46b26b74227
user: chs <chs%NetBSD.org@localhost>
date: Sun Jul 28 07:06:27 2002 +0000
description:
resync the MP and non-MP trap_subr's.
diffstat:
sys/arch/powerpc/powerpc/trap_subr.S | 24 +-
sys/arch/powerpc/powerpc/trap_subr_mp.S | 333 ++++++++++++++++++++-----------
2 files changed, 226 insertions(+), 131 deletions(-)
diffs (truncated from 617 to 300 lines):
diff -r 7898931c66ca -r d46b26b74227 sys/arch/powerpc/powerpc/trap_subr.S
--- a/sys/arch/powerpc/powerpc/trap_subr.S Sun Jul 28 07:05:53 2002 +0000
+++ b/sys/arch/powerpc/powerpc/trap_subr.S Sun Jul 28 07:06:27 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap_subr.S,v 1.25 2002/07/25 23:46:47 matt Exp $ */
+/* $NetBSD: trap_subr.S,v 1.26 2002/07/28 07:06:27 chs Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -40,11 +40,11 @@
#include "opt_altivec.h"
#ifdef ALTIVEC
-#define SAVE_VRSAVE(tf,b) \
+#define SAVE_VRSAVE(tf,b) \
mfspr b,SPR_VRSAVE; \
stw b,FRAME_VRSAVE+8(tf);
-#define RESTORE_VRSAVE(tf,b) \
+#define RESTORE_VRSAVE(tf,b) \
lwz b,FRAME_VRSAVE+8(tf); \
mtspr SPR_VRSAVE,b;
#else
@@ -687,7 +687,7 @@
/* Decide whether we return to user mode: */ \
lwz 3,savearea+4(0); \
mtcr 3; \
- bc 4,17,1f; /* branch if PSL_PR is false */ \
+ bc 4,17,1f; /* branch if PSL_PR is false */ \
/* Restore user SRs */ \
CPU601_KERN_LEAVE(2,3); \
RESTORE_USER_SRS(2,3); \
@@ -711,8 +711,8 @@
mfdar 30
mfdsisr 31
stmw 30,tempsave+16(0)
- .globl trapstart
-trapstart:
+ .globl _C_LABEL(trapstart)
+_C_LABEL(trapstart):
realtrap:
/* Test whether we already had PR set */
mfsrr1 1
@@ -743,8 +743,8 @@
trapagain:
addi 3,1,8
bl _C_LABEL(trap)
- .globl _C_LABEL(trapexit)
-_C_LABEL(trapexit):
+ .globl trapexit
+trapexit:
/* Disable interrupts: */
mfmsr 3
andi. 3,3,~PSL_EE@l
@@ -949,9 +949,9 @@
mtlr 6
lwz 6,IFRAME_R6(1)
lwz 5,IFRAME_R5(1)
- lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
+ lis 3,_C_LABEL(intr_depth)@ha
lwz 4,_C_LABEL(intr_depth)@l(3)
- addi 4,4,-1
+ addi 4,4,-1 /* adjust reentrancy count */
stw 4,_C_LABEL(intr_depth)@l(3)
lwz 4,IFRAME_R4(1)
lwz 3,IFRAME_R3(1)
@@ -1126,5 +1126,5 @@
icbi 0,9 /* and instruction caches */
blr
#endif /* IPKDB */
- .globl trapend
-trapend:
+ .globl _C_LABEL(trapend)
+_C_LABEL(trapend):
diff -r 7898931c66ca -r d46b26b74227 sys/arch/powerpc/powerpc/trap_subr_mp.S
--- a/sys/arch/powerpc/powerpc/trap_subr_mp.S Sun Jul 28 07:05:53 2002 +0000
+++ b/sys/arch/powerpc/powerpc/trap_subr_mp.S Sun Jul 28 07:06:27 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap_subr_mp.S,v 1.4 2001/06/23 02:36:15 matt Exp $ */
+/* $NetBSD: trap_subr_mp.S,v 1.5 2002/07/28 07:06:27 chs Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -38,6 +38,57 @@
* #include <powerpc/powerpc/trap_subr.S>
*/
+#ifdef ALTIVEC
+#define DSSALL /* assumes PSL is in cr registers */ \
+ bc+ 4,6,86f; /* branch is PSL_VEC is false */ \
+ dssall; /* stop datastreams */ \
+86:
+#define SAVE_VRSAVE(tf,b) \
+ mfspr b,SPR_VRSAVE; \
+ stw b,FRAME_VRSAVE+8(tf);
+
+#define RESTORE_VRSAVE(tf,b) \
+ lwz b,FRAME_VRSAVE+8(tf); \
+ mtspr SPR_VRSAVE,b;
+#else
+#define DSSALL
+#define SAVE_VRSAVE(tf,b)
+#define RESTORE_VRSAVE(tf,b)
+#endif
+#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
+ lwz sr,4(pmap); mtsr 1,sr; \
+ lwz sr,8(pmap); mtsr 2,sr; \
+ lwz sr,12(pmap); mtsr 3,sr; \
+ lwz sr,16(pmap); mtsr 4,sr; \
+ lwz sr,20(pmap); mtsr 5,sr; \
+ lwz sr,24(pmap); mtsr 6,sr; \
+ lwz sr,28(pmap); mtsr 7,sr; \
+ lwz sr,32(pmap); mtsr 8,sr; \
+ lwz sr,36(pmap); mtsr 9,sr; \
+ lwz sr,40(pmap); mtsr 10,sr; \
+ lwz sr,44(pmap); mtsr 11,sr; \
+ lwz sr,48(pmap); mtsr 12,sr; \
+ lwz sr,52(pmap); mtsr 13,sr; \
+ lwz sr,56(pmap); mtsr 14,sr; \
+ lwz sr,60(pmap); mtsr 15,sr;
+
+/*
+ * User SRs are loaded through a pointer to the current pmap.
+ */
+#define RESTORE_USER_SRS(pmap,sr) \
+ GET_CPUINFO(pmap); \
+ lwz pmap,CI_CURPM(pmap); \
+ lwzu sr,PM_SR(pmap); \
+ RESTORE_SRS(pmap,sr)
+
+/*
+ * Kernel SRs are loaded directly from kernel_pmap_
+ */
+#define RESTORE_KERN_SRS(pmap,sr) \
+ lis pmap,_C_LABEL(kernel_pmap_)@ha; \
+ lwzu sr,_C_LABEL(kernel_pmap_)+PM_SR@l(pmap); \
+ RESTORE_SRS(pmap,sr)
+
/*
* This code gets copied to all the trap vectors
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
@@ -55,11 +106,6 @@
/* Test whether we already had PR set */
mfsrr1 31
mtcr 31
- bc 4,17,1f /* branch if PSL_PR is clear */
- GET_CPUINFO(1)
- lwz 1,CI_CURPCB(1)
- addi 1,1,USPACE /* stack is top of user struct */
-1:
bla s_trap
_C_LABEL(trapsize) = .-_C_LABEL(trapcode)
@@ -80,11 +126,6 @@
/* Test whether we already had PR set */
mfsrr1 31
mtcr 31
- bc 4,17,1f /* branch if PSL_PR is clear */
- GET_CPUINFO(1)
- lwz 1,CI_CURPCB(1)
- addi 1,1,USPACE /* stack is top of user struct */
-1:
bla s_trap
_C_LABEL(alisize) = .-_C_LABEL(alitrap)
@@ -228,6 +269,24 @@
*/
.globl _C_LABEL(tlbimiss),_C_LABEL(tlbimsize)
_C_LABEL(tlbimiss):
+#ifdef PMAPDEBUG
+ mfspr 2,SPR_IMISS /* exception address */
+ li 1,24 /* get rid of the lower */
+ srw 2,2,1 /* 24 bits */
+ li 1,1 /* Load 1 */
+ cmpl 2,1,1 /* is it > 16MB */
+ blt 99f /* nope, skip saving these SPRs */
+ li 1,0xc0 /* arbitrary */
+ mfspr 2,SPR_HASH1
+ stw 2,0(1)
+ mfspr 2,SPR_HASH2
+ stw 2,4(1)
+ mfspr 2,SPR_IMISS
+ stw 2,8(1)
+ mfspr 2,SPR_ICMP
+ stw 2,12(1)
+99:
+#endif /* PMAPDEBUG */
mfspr 2,SPR_HASH1 /* get first pointer */
li 1,8
mfctr 0 /* save counter */
@@ -408,7 +467,7 @@
ba EXC_DSI
_C_LABEL(tlbdsmsize) = .-_C_LABEL(tlbdsmiss)
-#ifdef DDB
+#if defined(DDB) || defined(KGDB)
#define ddbsave 0xde0 /* primary save area for DDB */
/*
* In case of DDB we want a separate trap catcher for it
@@ -427,7 +486,7 @@
addi 1,1,ddbstk+INTSTK@l
bla ddbtrap
_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
-#endif /* DDB */
+#endif /* DDB || KGDB */
#ifdef IPKDB
#define ipkdbsave 0xde0 /* primary save area for IPKDB */
@@ -451,6 +510,35 @@
_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
#endif /* IPKDB */
+#ifdef CPU601_KERN_ENTRY_HOOK
+#define CPU601_KERN_ENTRY(_s1_,_s2_) \
+ mfpvr _s1_; \
+ srwi _s1_,_s1_,16; \
+ cmpi 0,_s1_,MPC601; \
+ bne 98f; /* skip if not 601 */ \
+ CPU601_KERN_ENTRY_HOOK(_s1_,_s2_); \
+98:
+#else
+#define CPU601_KERN_ENTRY(_s1_,_s2_) /* nothing */
+#endif
+
+#ifdef CPU601_KERN_LEAVE_HOOK
+#define CPU601_KERN_LEAVE(_pmap_,_s1_) \
+ mfpvr _s1_; \
+ srwi _s1_,_s1_,16; \
+ cmpi 0,_s1_,MPC601; \
+ bne 99f; /* skip if not 601 */ \
+ CPU601_KERN_LEAVE_HOOK(_pmap_,_s1_); \
+ xor _s1_,_s1_,_s1_; \
+ mtibatl 0,_s1_; /* obliterate BATs */ \
+ mtibatl 1,_s1_; \
+ mtibatl 2,_s1_; \
+ mtibatl 3,_s1_; \
+99:
+#else
+#define CPU601_KERN_LEAVE(_pmap_,_s1_) /* nothing */
+#endif
+
/*
* FRAME_SETUP assumes:
* SPRG1 SP (1)
@@ -481,7 +569,7 @@
stw 2,FRAME_2+8(1); \
GET_CPUINFO(2); \
lmw 28,savearea(2); \
- stmw 3,FRAME_3+8(1); \
+ stmw 3,FRAME_3+8(1); /* after this, r3-r31 can be used */ \
lmw 28,savearea+16(2); \
mfxer 3; \
mfctr 4; \
@@ -490,6 +578,7 @@
stw 3,FRAME_XER+8(1); \
stw 4,FRAME_CTR+8(1); \
stw 5,FRAME_EXC+8(1); \
+ SAVE_VRSAVE(2,6); \
stw 28,FRAME_DAR+8(1); \
stw 29,FRAME_DSISR+8(1); \
stw 30,FRAME_SRR0+8(1); \
@@ -502,6 +591,7 @@
lwz 4,FRAME_CTR+8(1); \
lwz 5,FRAME_XER+8(1); \
lwz 6,FRAME_LR+8(1); \
+ RESTORE_VRSAVE(1,8); \
GET_CPUINFO(7); \
stw 2,savearea(7); \
stw 3,savearea+4(7); \
@@ -511,8 +601,8 @@
mtlr 6; \
mtsprg 1,7; /* save cr */ \
lmw 2,FRAME_2+8(1); \
- lwz 0,FRAME_0+8(1); \
- lwz 1,FRAME_1+8(1); \
+ lwz 0,FRAME_0+8(1); /* restore r0 */ \
+ lwz 1,FRAME_1+8(1); /* restore old sp in r1 */ \
mtsprg 2,2; /* save r2 & r3 */ \
mtsprg 3,3; \
/* Disable translation, machine check and recoverability: */ \
@@ -525,13 +615,9 @@
lwz 3,savearea+4(2); \
mtcr 3; \
bc 4,17,1f; /* branch if PSL_PR is false */ \
-/* Restore user & kernel access SR: */ \
- GET_CPUINFO(2); \
- lwz 2,CI_CURPM(2); /* get real address of pmap */ \
- lwz 3,PM_USRSR(2); \
- mtsr USER_SR,3; \
- lwz 3,PM_KERNELSR(2); \
- mtsr KERNEL_SR,3; \
+/* Restore user SRs */ \
+ CPU601_KERN_LEAVE(2,3); \
+ RESTORE_USER_SRS(2,3); \
1: mfsprg 2,1; /* restore cr */ \
mtcr 2; \
GET_CPUINFO(2); \
@@ -554,13 +640,17 @@
mfdar 30
mfdsisr 31
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