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[src/trunk]: src/sys/arch/hpcmips switch from splvec to ipl_sr_bits.
details: https://anonhg.NetBSD.org/src/rev/97f03c26ec60
branches: trunk
changeset: 515009:97f03c26ec60
user: uch <uch%NetBSD.org@localhost>
date: Sat Sep 15 19:51:38 2001 +0000
description:
switch from splvec to ipl_sr_bits.
diffstat:
sys/arch/hpcmips/hpcmips/interrupt.c | 165 +++++++++++++++++++++++++---------
sys/arch/hpcmips/hpcmips/machdep.c | 7 +-
sys/arch/hpcmips/include/intr.h | 79 ++++-----------
sys/arch/hpcmips/tx/tx39.c | 12 +--
sys/arch/hpcmips/vr/vr.c | 12 +--
5 files changed, 149 insertions(+), 126 deletions(-)
diffs (truncated from 418 to 300 lines):
diff -r c5c88d715617 -r 97f03c26ec60 sys/arch/hpcmips/hpcmips/interrupt.c
--- a/sys/arch/hpcmips/hpcmips/interrupt.c Sat Sep 15 19:32:14 2001 +0000
+++ b/sys/arch/hpcmips/hpcmips/interrupt.c Sat Sep 15 19:51:38 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.2 2001/09/15 14:08:15 uch Exp $ */
+/* $NetBSD: interrupt.c,v 1.3 2001/09/15 19:51:38 uch Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -47,17 +47,28 @@
#include <machine/locore.h> /* mips3_cp0_*() */
#include <machine/sysconf.h>
-struct hpcmips_soft_intrhand *softnet_intrhand;
+#ifdef DEBUG
+#define STATIC
+#else
+#define STATIC static
+#endif
-#if 0
-/*
- * NetBSD/hpcmips currently using splvec structure for this. XXX.
- */
+#if defined(VR41XX) && defined(TX39XX)
+STATIC void (*__cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+#define VR_INTR vr_intr
+#define TX_INTR tx_intr
+#elif defined(VR41XX)
+#define VR_INTR cpu_intr
+#elif defined(TX39XX)
+#define TX_INTR cpu_intr
+#endif
+
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
-const u_int32_t ipl_sr_bits[_IPL_N] = {
+#ifdef VR41XX
+const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
0, /* IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
@@ -87,7 +98,43 @@
MIPS_INT_MASK_0|
MIPS_INT_MASK_1, /* IPL_{CLOCK,HIGH} */
};
-#endif
+#endif /* VR41XX */
+
+#ifdef TX39XX
+const u_int32_t __ipl_sr_bits_tx[_IPL_N] = {
+ 0, /* IPL_NONE */
+
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
+
+ MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_4, /* IPL_BIO */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_4, /* IPL_NET */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */
+
+ MIPS_SOFT_INT_MASK_0|
+ MIPS_SOFT_INT_MASK_1|
+ MIPS_INT_MASK_2|
+ MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */
+};
+#endif /* TX39XX */
const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
@@ -96,51 +143,81 @@
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
};
+const u_int32_t *ipl_sr_bits;
+struct hpcmips_soft_intrhand *softnet_intrhand;
struct hpcmips_soft_intr hpcmips_soft_intrs[_IPL_NSOFT];
+STATIC void softintr(u_int32_t);
void
+intr_init()
+{
+#if defined(VR41XX) && defined(TX39XX)
+ __cpu_intr = CPUISMIPS3 ? vr_intr : tx_intr;
+ ipl_sr_bits = CPUISMIPS3 ? __ipl_sr_bits_vr : __ipl_sr_bits_tx;
+#elif defined(VR41XX)
+ ipl_sr_bits = __ipl_sr_bits_vr;
+#elif defined(TX39XX)
+ ipl_sr_bits = __ipl_sr_bits_tx;
+#endif
+}
+
+#if defined(VR41XX) && defined(TX39XX)
+void
cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{
+
+ (*__cpu_intr)(status, caust, pc, ipending);
+}
+#endif /* VR41XX && TX39XX */
+
+#ifdef VR41XX
+void
+VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
+{
+ uvmexp.intrs++;
+
+ if (ipending & MIPS_INT_MASK_5) {
+ /*
+ * Writing a value to the Compare register,
+ * as a side effect, clears the timer
+ * interrupt request.
+ */
+ mips3_cp0_compare_write(mips3_cp0_count_read());
+ }
+
+ if (ipending & MIPS3_HARD_INT_MASK)
+ _splset((*platform.iointr)(status, cause, pc, ipending));
+
+ softintr(ipending);
+}
+#endif /* VR41XX */
+
+#ifdef TX39XX
+void
+TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
+{
+ uvmexp.intrs++;
+
+ if (ipending & MIPS_HARD_INT_MASK)
+ _splset((*platform.iointr)(status, cause, pc, ipending));
+
+ softintr(ipending);
+}
+#endif /* TX39XX */
+
+/*
+ * softintr:
+ *
+ * dispatch pending software interrupt handler.
+ */
+void
+softintr(u_int32_t ipending)
+{
struct hpcmips_soft_intr *asi;
struct hpcmips_soft_intrhand *sih;
int i, s;
- uvmexp.intrs++;
-
-#ifdef VR41XX
-#ifdef TX39XX
- if (CPUISMIPS3)
-#endif /* TX39XX */
- if (ipending & MIPS_INT_MASK_5) {
- /*
- * Writing a value to the Compare register,
- * as a side effect, clears the timer
- * interrupt request.
- */
- mips3_cp0_compare_write(mips3_cp0_count_read());
- }
-#endif
-
- /* Process clock and I/O interrupts. */
-#if defined(VR41XX)
-#if defined(TX39XX)
- if (CPUISMIPS3)
-#endif /* TX39XX */
- if (ipending & MIPS3_HARD_INT_MASK)
- _splset((*platform.iointr)(status, cause, pc,
- ipending));
-#endif /* VR41XX */
-
-#if defined(TX39XX)
-#if defined(VR41XX)
- if (!CPUISMIPS3)
-#endif /* VR41XX */
- if (ipending & MIPS_HARD_INT_MASK)
- _splset((*platform.iointr)(status, cause, pc,
- ipending));
-#endif /* TX39XX */
-
- ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
+ ipending &= (MIPS_SOFT_INT_MASK_1 | MIPS_SOFT_INT_MASK_0);
if (ipending == 0)
return;
diff -r c5c88d715617 -r 97f03c26ec60 sys/arch/hpcmips/hpcmips/machdep.c
--- a/sys/arch/hpcmips/hpcmips/machdep.c Sat Sep 15 19:32:14 2001 +0000
+++ b/sys/arch/hpcmips/hpcmips/machdep.c Sat Sep 15 19:51:38 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.60 2001/09/15 14:08:15 uch Exp $ */
+/* $NetBSD: machdep.c,v 1.61 2001/09/15 19:51:38 uch Exp $ */
/*-
* Copyright (c) 1999 Shin Takemura, All rights reserved.
@@ -72,7 +72,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.60 2001/09/15 14:08:15 uch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.61 2001/09/15 19:51:38 uch Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
#include "opt_vr41xx.h"
@@ -177,8 +177,6 @@
unsigned ssir; /* schedules software interrupt */
-struct splvec splvec; /* XXX will go XXX */
-
void mach_init(int, char *[], struct bootinfo *);
static struct bootinfo bi_copy;
@@ -341,6 +339,7 @@
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
+ intr_init();
mips_vector_init();
/*
diff -r c5c88d715617 -r 97f03c26ec60 sys/arch/hpcmips/include/intr.h
--- a/sys/arch/hpcmips/include/intr.h Sat Sep 15 19:32:14 2001 +0000
+++ b/sys/arch/hpcmips/include/intr.h Sat Sep 15 19:51:38 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.12 2001/09/15 15:04:45 uch Exp $ */
+/* $NetBSD: intr.h,v 1.13 2001/09/15 19:51:39 uch Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -77,11 +77,12 @@
#ifdef _KERNEL
#ifndef _LOCORE
-
#include <mips/cpuregs.h>
+extern const u_int32_t *ipl_sr_bits;
extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT];
+void intr_init(void);
int _splraise(int);
int _spllower(int);
int _splset(int);
@@ -90,48 +91,27 @@
void _setsoftintr(int);
void _clrsoftintr(int);
-#define splhigh() _splraise(MIPS_INT_MASK)
-#define spl0() (void)_spllower(0)
-#define splx(s) (void)_splset(s)
-#define splbio() (_splraise(splvec.splbio))
-#define splnet() (_splraise(splvec.splnet))
-#define spltty() (_splraise(splvec.spltty))
-#define splserial() spltty()
-#define splvm() (_splraise(splvec.splvm))
-#define splclock() (_splraise(splvec.splclock))
-#define splstatclock() (_splraise(splvec.splstatclock))
-#define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
-#define splsoft() _splraise(MIPS_SOFT_INT_MASK_0)
-#define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0)
-#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-#define splsoftserial() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
-
-#define splsched() splhigh()
-#define spllock() splhigh()
+#define splhigh() _splraise(ipl_sr_bits[IPL_HIGH])
+#define spl0() (void) _spllower(0)
+#define splx(s) (void) _splset(s)
+#define splbio() _splraise(ipl_sr_bits[IPL_BIO])
+#define splnet() _splraise(ipl_sr_bits[IPL_NET])
+#define spltty() _splraise(ipl_sr_bits[IPL_TTY])
+#define splserial() _splraise(ipl_sr_bits[IPL_SERIAL])
+#define splvm() spltty()
+#define splclock() _splraise(ipl_sr_bits[IPL_CLOCK])
+#define splstatclock() splclock()
-struct splvec {
- int splbio;
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