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[src/trunk]: src/sys/arch/sparc64/include Don't need to flush the d$ for MMU ...
details: https://anonhg.NetBSD.org/src/rev/f7fa2a42a510
branches: trunk
changeset: 526085:f7fa2a42a510
user: eeh <eeh%NetBSD.org@localhost>
date: Wed Apr 24 23:54:24 2002 +0000
description:
Don't need to flush the d$ for MMU bypass accesses.
diffstat:
sys/arch/sparc64/include/ctlreg.h | 320 +++++++++++--------------------------
1 files changed, 94 insertions(+), 226 deletions(-)
diffs (truncated from 533 to 300 lines):
diff -r 58017bb4ea4c -r f7fa2a42a510 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Wed Apr 24 23:04:08 2002 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Wed Apr 24 23:54:24 2002 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: ctlreg.h,v 1.29 2002/01/14 20:44:30 eeh Exp $ */
+/* $NetBSD: ctlreg.h,v 1.30 2002/04/24 23:54:24 eeh Exp $ */
/*
- * Copyright (c) 1996-2001 Eduardo Horvath
+ * Copyright (c) 1996-2002 Eduardo Horvath
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -478,20 +478,10 @@
{
register unsigned int _lduba_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" lduba [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; wr %%g0, 0x82, %%asi" :
- "=&r" (_lduba_v), "=r" (loc):
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; "
-" lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lduba_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; "
+ " lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
+ "=r" (_lduba_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lduba_v);
}
#else
@@ -502,15 +492,13 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; "
-" sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; "
+ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
+" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; "
" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
" membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lduba_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
" or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) :
@@ -528,20 +516,10 @@
{
register unsigned int _lduha_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" lduha [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v), "=r" (loc) :
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
-" wr %%g0, 0x82, %%asi" :
- "=r" (_lduha_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
+ " wr %%g0, 0x82, %%asi" :
+ "=r" (_lduha_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lduha_v);
}
#else
@@ -553,14 +531,13 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; "
+ __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
+" rdpr %%pstate,%1; wrpr %1,8,%%pstate; "
" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
" membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lduha_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
" or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) :
@@ -578,19 +555,9 @@
{
register unsigned int _lda_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" lda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" :
+ "=r" (_lda_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
@@ -600,20 +567,10 @@
{
register int _lda_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" ldswa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; "
-" ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; "
+ " ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
+ "=r" (_lda_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
#else /* __arch64__ */
@@ -626,13 +583,11 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
-" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; "
-" sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; "
-" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %5; membar #Sync; "
+" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; "
+" lda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; "
" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
" or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
@@ -651,13 +606,12 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
-" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;"
+" wrpr %1,8,%%pstate; sllx %3,32,%0;"
" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
-" wr %%g0, 0x82, %%asi" :
+" membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
" or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
@@ -675,20 +629,10 @@
{
register long long _lda_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" ldda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (loc) :
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; "
-" ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; "
+ " ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
+ "=r" (_lda_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
#else
@@ -701,13 +645,11 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
-" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;"
-" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
-" wr %%g0, 0x82, %%asi" :
+" wrpr %1,8,%%pstate; sllx %3,32,%0; or %0,%2,%0; membar #Sync;"
+" ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
" or %0,%1,%0; ldda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
@@ -725,20 +667,10 @@
{
register unsigned long _lda_v;
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; "
-" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
-" ldxa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
- "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; "
-" ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; "
+ " ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
+ "=r" (_lda_v) :
+ "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
#else
@@ -750,14 +682,13 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; "
-" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; "
-" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; "
-" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
+ __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; "
+" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; "
+" ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; "
" srlx %0,32,%1; srl %0,0,%0; wr %%g0, 0x82, %%asi" :
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi), "n" (ASI_DCACHE_TAG));
+ "r" (asi));
} else {
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; "
@@ -775,19 +706,10 @@
static __inline__ void
stba(paddr_t loc, int asi, u_char value)
{
- if (PHYS_ASI(asi)) {
- __asm __volatile("wr %3,%%g0,%%asi; stba %1,[%2]%%asi;"
-" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
-" wr %%g0, 0x82, %%asi" :
- "=&r" (loc) :
- "r" ((int)(value)), "r" ((unsigned long)(loc)),
- "r" (asi), "n" (ASI_DCACHE_TAG));
- } else {
- __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; "
-" wr %%g0, 0x82, %%asi" : :
- "r" ((int)(value)), "r" ((unsigned long)(loc)),
- "r" (asi));
- }
+ __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; "
+ " wr %%g0, 0x82, %%asi" : :
+ "r" ((int)(value)), "r" ((unsigned long)(loc)),
+ "r" (asi));
}
#else
static __inline__ void
@@ -797,13 +719,12 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;"
-" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; "
-" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
-" wr %%g0, 0x82, %%asi" :
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