[src/trunk]: src/sys/arch/arm/arm32 When doing PREREAD sync operations, if th...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/41485c1e3795
branches:  trunk
changeset: 535320:41485c1e3795
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Wed Aug 14 22:56:55 2002 +0000

description:
When doing PREREAD sync operations, if the start and end addresses
of the range are aligned to a cacheline boundary, when do a dcache-inv
operation, rather than a dcache-wbinv operation.

XXX It could be a little smarter (align using wbinv, inv, then finish
up using wbinv), but even this simple change is good for a nearly 40%
improvement in my test case on XScale.

diffstat:

 sys/arch/arm/arm32/bus_dma.c |  29 +++++++++++++----------------
 1 files changed, 13 insertions(+), 16 deletions(-)

diffs (57 lines):

diff -r d0c17216c0ac -r 41485c1e3795 sys/arch/arm/arm32/bus_dma.c
--- a/sys/arch/arm/arm32/bus_dma.c      Wed Aug 14 22:53:19 2002 +0000
+++ b/sys/arch/arm/arm32/bus_dma.c      Wed Aug 14 22:56:55 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_dma.c,v 1.17 2002/08/14 20:50:37 thorpej Exp $     */
+/*     $NetBSD: bus_dma.c,v 1.18 2002/08/14 22:56:55 thorpej Exp $     */
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -353,11 +353,10 @@
                break;
 
        case BUS_DMASYNC_PREREAD:
-#if 1
-               cpu_dcache_wbinv_range(addr, len);
-#else
-               cpu_dcache_inv_range(addr, len);
-#endif
+               if (((addr | len) & arm_dcache_align_mask) == 0)
+                       cpu_dcache_inv_range(addr, len);
+               else
+                       cpu_dcache_wbinv_range(addr, len);
                break;
 
        case BUS_DMASYNC_PREWRITE:
@@ -399,11 +398,10 @@
                        break;
 
                case BUS_DMASYNC_PREREAD:
-#if 1
-                       cpu_dcache_wbinv_range(maddr, minlen);
-#else
-                       cpu_dcache_inv_range(maddr, minlen);
-#endif
+                       if (((maddr | minlen) & arm_dcache_align_mask) == 0)
+                               cpu_dcache_inv_range(maddr, minlen);
+                       else
+                               cpu_dcache_wbinv_range(maddr, minlen);
                        break;
 
                case BUS_DMASYNC_PREWRITE:
@@ -448,11 +446,10 @@
                        break;
 
                case BUS_DMASYNC_PREREAD:
-#if 1
-                       cpu_dcache_wbinv_range(addr, minlen);
-#else
-                       cpu_dcache_inv_range(addr, minlen);
-#endif
+                       if (((addr | minlen) & arm_dcache_align_mask) == 0)
+                               cpu_dcache_inv_range(addr, minlen);
+                       else
+                               cpu_dcache_wbinv_range(addr, minlen);
                        break;
 
                case BUS_DMASYNC_PREWRITE: