[src/trunk]: src/sys/arch/powerpc/include Include bit definitions for the Deb...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d53d2fea9d03
branches:  trunk
changeset: 516747:d53d2fea9d03
user:      simonb <simonb%NetBSD.org@localhost>
date:      Mon Oct 29 02:02:19 2001 +0000

description:
Include bit definitions for the Debug Status Register; from Artem Belevich
at Riverstone Networks.

diffstat:

 sys/arch/powerpc/include/spr.h |  15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diffs (25 lines):

diff -r d128eb9ba613 -r d53d2fea9d03 sys/arch/powerpc/include/spr.h
--- a/sys/arch/powerpc/include/spr.h    Mon Oct 29 02:00:01 2001 +0000
+++ b/sys/arch/powerpc/include/spr.h    Mon Oct 29 02:02:19 2001 +0000
@@ -168,6 +168,21 @@
 #define        SPR_SRR2                0x3de   /* 4.. Save/Restore Register 2 */
 #define        SPR_SRR3                0x3df   /* 4.. Save/Restore Register 3 */
 #define        SPR_DBSR                0x3f0   /* 4.. Debug Status Register */
+#define          DBSR_IC                 0x80000000 /* Instruction completion debug event */
+#define          DBSR_BT                 0x40000000 /* Branch Taken debug event */
+#define          DBSR_EDE                0x20000000 /* Exception debug event */
+#define          DBSR_TIE                0x10000000 /* Trap Instruction debug event */
+#define          DBSR_UDE                0x08000000 /* Unconditional debug event */
+#define          DBSR_IA1                0x04000000 /* IAC1 debug event */
+#define          DBSR_IA2                0x02000000 /* IAC2 debug event */
+#define          DBSR_DR1                0x01000000 /* DAC1 Read debug event */
+#define          DBSR_DW1                0x00800000 /* DAC1 Write debug event */
+#define          DBSR_DR2                0x00400000 /* DAC2 Read debug event */
+#define          DBSR_DW2                0x00200000 /* DAC2 Write debug event */
+#define          DBSR_IDE                0x00100000 /* Imprecise debug event */
+#define          DBSR_IA3                0x00080000 /* IAC3 debug event */
+#define          DBSR_IA4                0x00040000 /* IAC4 debug event */
+#define          DBSR_MRR                0x00000300 /* Most recent reset */
 #define        SPR_HID0                0x3f0   /* ..8 Hardware Implementation Register 0 */
 #define        SPR_HID1                0x3f1   /* ..8 Hardware Implementation Register 1 */
 #define        SPR_DBCR0               0x3f2   /* 4.. Debug Control Register 0 */