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[src/trunk]: src/sys/arch/powerpc/ibm4xx Clean up some white space niggles.
details: https://anonhg.NetBSD.org/src/rev/43b9c6447edd
branches: trunk
changeset: 533934:43b9c6447edd
user: simonb <simonb%NetBSD.org@localhost>
date: Thu Jul 11 01:38:48 2002 +0000
description:
Clean up some white space niggles.
diffstat:
sys/arch/powerpc/ibm4xx/4xx_trap_subr.S | 34 ++++++++++----------
sys/arch/powerpc/ibm4xx/clock.c | 12 +++---
sys/arch/powerpc/ibm4xx/copyinstr.c | 4 +-
sys/arch/powerpc/ibm4xx/copyoutstr.c | 4 +-
sys/arch/powerpc/ibm4xx/cpu.c | 54 ++++++++++++++++----------------
sys/arch/powerpc/ibm4xx/intr.c | 14 ++++----
sys/arch/powerpc/ibm4xx/mainbus.c | 4 +-
sys/arch/powerpc/ibm4xx/pmap.c | 37 +++++++++++-----------
sys/arch/powerpc/ibm4xx/trap.c | 36 +++++++++++-----------
sys/arch/powerpc/ibm4xx/trap_subr.S | 46 ++++++++++++++--------------
10 files changed, 122 insertions(+), 123 deletions(-)
diffs (truncated from 872 to 300 lines):
diff -r 3cbd7434512b -r 43b9c6447edd sys/arch/powerpc/ibm4xx/4xx_trap_subr.S
--- a/sys/arch/powerpc/ibm4xx/4xx_trap_subr.S Thu Jul 11 01:29:28 2002 +0000
+++ b/sys/arch/powerpc/ibm4xx/4xx_trap_subr.S Thu Jul 11 01:38:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: 4xx_trap_subr.S,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
+/* $NetBSD: 4xx_trap_subr.S,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -35,7 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-/* This file provides necessary handlers for 405GP CPU
+/* This file provides necessary handlers for 405GP CPU
* It should be included in locore.S after powerpc/powerpc/trap_subr.S
*/
@@ -57,7 +57,7 @@
pithandler:
rfi
ba . /* Protect against prefetch */
-
+
wdoghandler:
rfi
ba . /* Protect against prefetch */
@@ -66,15 +66,15 @@
#define tlbsave 0x3000
#define tlbstack tlbsave+tlbstacksize
-/* If an unaligned excception (0x600) and DTLB miss exception (0x1100)
- occur at the same time, the interrupt vector offsets of the two
+/* If an unaligned excception (0x600) and DTLB miss exception (0x1100)
+ occur at the same time, the interrupt vector offsets of the two
exceptions are logically OR'ed together to produce 0x1700.
See PPC405GP Rev D/E Errata item 51 */
-
+
.globl _C_LABEL(errata51handler),_C_LABEL(errata51size)
_C_LABEL(errata51handler):
ba 0x1100
-_C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
+_C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
.globl _C_LABEL(tlbdmiss4xx),_C_LABEL(tlbdm4size)
_C_LABEL(tlbdmiss4xx):
@@ -83,16 +83,16 @@
mfesr r31
stmw r30,16+tlbsave(0)
bla s4xx_miss
-_C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
+_C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
.globl _C_LABEL(tlbimiss4xx),_C_LABEL(tlbim4size)
-_C_LABEL(tlbimiss4xx):
+_C_LABEL(tlbimiss4xx):
STANDARD_PROLOG(tlbsave)
mfsrr0 r30 /* XXX Get fault address */
mfesr r31
stmw r30,16+tlbsave(0)
bla s4xx_miss
-_C_LABEL(tlbim4size) = .-_C_LABEL(tlbdmiss4xx)
+_C_LABEL(tlbim4size) = .-_C_LABEL(tlbdmiss4xx)
s4xx_miss:
.globl _C_LABEL(pmap_tlbmiss)
@@ -106,7 +106,7 @@
mtpid r30
beq 1f
- /*
+ /*
* The kernel we want to switch to is not in the TLB.
* To solve this problem, we will simulate a kernel
* fault on the kernel stack and let the miss handler
@@ -121,14 +121,14 @@
lis r1,tlbstack@ha
addi r1,r1,tlbstack@l
stw r30,4(1)
-
+
FRAME_SETUP(tlbsave)
/* Take an explicit fault at (kernelstack,pid) */
lwz r3, tlbstack+4(0)
li r4,KERNEL_PID
bl _C_LABEL(pmap_tlbmiss)
- /*
+ /*
* We can retry the old fault or switch stacks and
* take it now. It's easier to retry.
*/
@@ -138,7 +138,7 @@
/* kernel stack not in the pmap? we should panic */
trap
ba trapagain
-1:
+1:
FRAME_SETUP(tlbsave)
lwz r3,FRAME_DEAR+8(1)
lwz r4,FRAME_PID+8(1)
@@ -149,10 +149,10 @@
/* XXX DEBUG -- make sure we're not on tlbstack */
addi r7,r1,-tlbsave
twllei r7,(tlbstacksize)
-
- /* PTE not found, time to cause a fault */
+
+ /* PTE not found, time to cause a fault */
ba trapagain
-2:
+2:
FRAME_LEAVE(tlbsave)
rfi
ba . /* Protect against prefetch */
diff -r 3cbd7434512b -r 43b9c6447edd sys/arch/powerpc/ibm4xx/clock.c
--- a/sys/arch/powerpc/ibm4xx/clock.c Thu Jul 11 01:29:28 2002 +0000
+++ b/sys/arch/powerpc/ibm4xx/clock.c Thu Jul 11 01:38:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.2 2002/03/15 21:12:07 eeh Exp $ */
+/* $NetBSD: clock.c,v 1.3 2002/07/11 01:38:48 simonb Exp $ */
/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
/*
@@ -64,14 +64,14 @@
/* Stat clock runs at ~ 95Hz */
#define PERIOD_POWER 21
#define TCR_PERIOD TCR_FP_2_21
-#endif
+#endif
void
stat_intr(struct clockframe *frame)
{
extern u_long intrcnt[];
-
+
mtspr(SPR_TSR, TSR_FIS); /* Clear TSR[FIS] */
intrcnt[CNT_STATCLOCK]++;
statclock(frame);
@@ -132,12 +132,12 @@
cpu_initclocks(void)
{
ticks_per_intr = ticks_per_sec / hz;
- stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
+ stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
printf("Setting PIT to %ld/%d = %ld\n", ticks_per_sec, hz, ticks_per_intr);
asm volatile ("mftb %0" : "=r"(lasttb));
mtspr(SPR_PIT, ticks_per_intr);
/* Enable PIT & FIT(2^17c = 0.655ms) interrupts and auto-reload */
- mtspr(SPR_TCR, TCR_PIE | TCR_ARE | TCR_FIE | TCR_PERIOD);
+ mtspr(SPR_TCR, TCR_PIE | TCR_ARE | TCR_FIE | TCR_PERIOD);
}
void
@@ -145,7 +145,7 @@
{
unsigned int processor_freq;
- if (board_info_get("processor-frequency",
+ if (board_info_get("processor-frequency",
&processor_freq, sizeof(processor_freq)) == -1)
panic("no processor-frequency");
diff -r 3cbd7434512b -r 43b9c6447edd sys/arch/powerpc/ibm4xx/copyinstr.c
--- a/sys/arch/powerpc/ibm4xx/copyinstr.c Thu Jul 11 01:29:28 2002 +0000
+++ b/sys/arch/powerpc/ibm4xx/copyinstr.c Thu Jul 11 01:38:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: copyinstr.c,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
+/* $NetBSD: copyinstr.c,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -81,7 +81,7 @@
"sync; isync;"
"addi %3,%3,1;" /* Inc len */
"or. %2,%2,%2;"
- "bdnzf 2,1b;" /*
+ "bdnzf 2,1b;" /*
* while(ctr-- && !zero)
*/
diff -r 3cbd7434512b -r 43b9c6447edd sys/arch/powerpc/ibm4xx/copyoutstr.c
--- a/sys/arch/powerpc/ibm4xx/copyoutstr.c Thu Jul 11 01:29:28 2002 +0000
+++ b/sys/arch/powerpc/ibm4xx/copyoutstr.c Thu Jul 11 01:38:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: copyoutstr.c,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
+/* $NetBSD: copyoutstr.c,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -81,7 +81,7 @@
"sync; isync;"
"addi %3,%3,1;" /* Inc len */
"or. %2,%2,%2;"
- "bdnzf 2,1b;" /*
+ "bdnzf 2,1b;" /*
* while(ctr-- && !zero)
*/
diff -r 3cbd7434512b -r 43b9c6447edd sys/arch/powerpc/ibm4xx/cpu.c
--- a/sys/arch/powerpc/ibm4xx/cpu.c Thu Jul 11 01:29:28 2002 +0000
+++ b/sys/arch/powerpc/ibm4xx/cpu.c Thu Jul 11 01:38:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.2 2002/03/15 21:12:07 eeh Exp $ */
+/* $NetBSD: cpu.c,v 1.3 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -90,7 +90,7 @@
/* make sure that we're looking for a CPU */
if (strcmp(maa->mb_name, cf->cf_driver->cd_name) != 0)
- return (0);
+ return (0);
return !cpufound;
}
@@ -103,7 +103,7 @@
struct cputab *cp = models;
unsigned int processor_freq;
- if (board_info_get("processor-frequency",
+ if (board_info_get("processor-frequency",
&processor_freq, sizeof(processor_freq)) == -1)
panic("no processor-frequency");
@@ -139,9 +139,9 @@
cpu_probe_cache();
- printf("Instruction cache size %d line size %d\n",
+ printf("Instruction cache size %d line size %d\n",
curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size);
- printf("Data cache size %d line size %d\n",
+ printf("Data cache size %d line size %d\n",
curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size);
#ifdef DEBUG
@@ -153,7 +153,7 @@
/* Initialize ECC error-logging handler. This is always enabled,
* but it will never be called on systems that do not have ECC
* enabled by POST code in the bootloader.
- */
+ */
printf("Enabling ecc handler\n");
intr_ecc_tb = 0;
@@ -164,8 +164,8 @@
}
/*
- * This routine must be explicitly called to initialize the
- * CPU cache information so cache flushe and memcpy operation
+ * This routine must be explicitly called to initialize the
+ * CPU cache information so cache flushe and memcpy operation
* work.
*/
void
@@ -174,7 +174,7 @@
int version;
/*
- * First we need to identify the cpu and determine the
+ * First we need to identify the cpu and determine the
* cache line size, or things like memset/memcpy may lose
* badly.
*/
@@ -233,9 +233,9 @@
curcpu()->ci_ci.icache_line_size = 32;
break;
default:
- /*
- * Unknown CPU type. For safety we'll specify a
- * cache with a 4-byte line size. That way cache
+ /*
+ * Unknown CPU type. For safety we'll specify a
+ * cache with a 4-byte line size. That way cache
* flush routines won't miss any lines.
*/
curcpu()->ci_ci.dcache_line_size = 4;
@@ -318,7 +318,7 @@
if (board_info_get("mem-size", &memsiz, sizeof(memsiz)) == -1)
panic("no mem-size");
-
+
/* This code needs to be improved to handle double-bit errors */
/* in some intelligent fashion. */
@@ -328,27 +328,27 @@
mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR);
ear = mfdcr(DCR_SDRAM0_CFGDATA);
- /* Always clear the error to stop the intr ASAP. */
+ /* Always clear the error to stop the intr ASAP. */
mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
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