[src/trunk]: src/sys/arch/macppc Make spl functions no-inline. This saves si...

[tsubai <tsubai%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/072c8125a9b3
branches:  trunk
changeset: 499799:072c8125a9b3
user:      tsubai <tsubai%NetBSD.org@localhost>
date:      Wed Nov 29 17:55:52 2000 +0000

description:
Make spl functions no-inline.  This saves size and even it runs faster on
some systems.

diffstat:

 sys/arch/macppc/include/intr.h   |  75 +++------------------------------------
 sys/arch/macppc/macppc/extintr.c |  60 ++++++++++++++++++++++++++++++-
 2 files changed, 65 insertions(+), 70 deletions(-)

diffs (178 lines):

diff -r 22d56ed13656 -r 072c8125a9b3 sys/arch/macppc/include/intr.h
--- a/sys/arch/macppc/include/intr.h    Wed Nov 29 16:44:14 2000 +0000
+++ b/sys/arch/macppc/include/intr.h    Wed Nov 29 17:55:52 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intr.h,v 1.8 2000/08/22 19:46:29 thorpej Exp $ */
+/*     $NetBSD: intr.h,v 1.9 2000/11/29 17:55:52 tsubai Exp $  */
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -82,74 +82,13 @@
 void clearsoftnet __P((void));
 int  splsoftnet   __P((void));
 
-void do_pending_int __P((void));
-
-static __inline int splraise __P((int));
-static __inline int spllower __P((int));
-static __inline void splx __P((int));
-static __inline void softintr __P((int));
-
-extern volatile int cpl, ipending, astpending, tickspending;
-extern int imask[];
-
-/*
- *  Reorder protection in the following inline functions is
- * achived with the "eieio" instruction which the assembler
- * seems to detect and then doen't move instructions past....
- */
-static __inline int
-splraise(ncpl)
-       int ncpl;
-{
-       int ocpl;
-
-       __asm__ volatile("sync; eieio\n");      /* don't reorder.... */
-       ocpl = cpl;
-       cpl = ocpl | ncpl;
-       __asm__ volatile("sync; eieio\n");      /* reorder protect */
-       return (ocpl);
-}
-
-static __inline void
-splx(ncpl)
-       int ncpl;
-{
+int splraise __P((int));
+int spllower __P((int));
+void splx __P((int));
+void softintr __P((int));
 
-       __asm__ volatile("sync; eieio\n");      /* reorder protect */
-       cpl = ncpl;
-       if (ipending & ~ncpl)
-               do_pending_int();
-       __asm__ volatile("sync; eieio\n");      /* reorder protect */
-}
-
-static __inline int
-spllower(ncpl)
-       int ncpl;
-{
-       int ocpl;
-
-       __asm__ volatile("sync; eieio\n");      /* reorder protect */
-       ocpl = cpl;
-       cpl = ncpl;
-       if (ipending & ~ncpl)
-               do_pending_int();
-       __asm__ volatile("sync; eieio\n");      /* reorder protect */
-       return (ocpl);
-}
-
-/* Following code should be implemented with lwarx/stwcx to avoid
- * the disable/enable. i need to read the manual once more.... */
-static __inline void
-softintr(ipl)
-       int ipl;
-{
-       int msrsave;
-
-       __asm__ volatile("mfmsr %0" : "=r"(msrsave));
-       __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
-       ipending |= 1 << ipl;
-       __asm__ volatile("mtmsr %0" :: "r"(msrsave));
-}
+extern volatile int astpending, tickspending;
+extern int imask[];
 
 #define ICU_LEN                64
 
diff -r 22d56ed13656 -r 072c8125a9b3 sys/arch/macppc/macppc/extintr.c
--- a/sys/arch/macppc/macppc/extintr.c  Wed Nov 29 16:44:14 2000 +0000
+++ b/sys/arch/macppc/macppc/extintr.c  Wed Nov 29 17:55:52 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: extintr.c,v 1.15 2000/08/20 06:56:42 tsubai Exp $      */
+/*     $NetBSD: extintr.c,v 1.16 2000/11/29 17:55:52 tsubai Exp $      */
 
 /*-
  * Copyright (c) 1995 Per Fogelstrom
@@ -74,6 +74,8 @@
 static __inline int openpic_read_irq __P((int));
 static __inline void openpic_eoi __P((int));
 
+static void do_pending_int __P((void));
+
 unsigned int imen = 0xffffffff;
 volatile int cpl, ipending, astpending, tickspending;
 int imask[NIPL];
@@ -610,7 +612,7 @@
        splx(pcpl);     /* Process pendings. */
 }
 
-void
+static void
 do_pending_int()
 {
        struct intrhand *ih;
@@ -672,6 +674,60 @@
        processing = 0;
 }
 
+int
+splraise(ncpl)
+       int ncpl;
+{
+       int ocpl;
+
+       asm volatile("sync; eieio\n");  /* don't reorder.... */
+       ocpl = cpl;
+       cpl = ocpl | ncpl;
+       asm volatile("sync; eieio\n");  /* reorder protect */
+       return ocpl;
+}
+
+void
+splx(ncpl)
+       int ncpl;
+{
+
+       asm volatile("sync; eieio\n");  /* reorder protect */
+       cpl = ncpl;
+       if (ipending & ~ncpl)
+               do_pending_int();
+       asm volatile("sync; eieio\n");  /* reorder protect */
+}
+
+int
+spllower(ncpl)
+       int ncpl;
+{
+       int ocpl;
+
+       asm volatile("sync; eieio\n");  /* reorder protect */
+       ocpl = cpl;
+       cpl = ncpl;
+       if (ipending & ~ncpl)
+               do_pending_int();
+       asm volatile("sync; eieio\n");  /* reorder protect */
+       return ocpl;
+}
+
+/* Following code should be implemented with lwarx/stwcx to avoid
+ * the disable/enable. i need to read the manual once more.... */
+void
+softintr(ipl)
+       int ipl;
+{
+       int msrsave;
+
+       asm volatile("mfmsr %0" : "=r"(msrsave));
+       asm volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
+       ipending |= 1 << ipl;
+       asm volatile("mtmsr %0" :: "r"(msrsave));
+}
+
 void
 openpic_init()
 {