[src/trunk]: src/sys/arch/arm/arm Add code to run the XScale cache in write-t...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/478459480139
branches:  trunk
changeset: 518248:478459480139
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Mon Nov 26 22:26:44 2001 +0000

description:
Add code to run the XScale cache in write-though mode, and do so
for now...

diffstat:

 sys/arch/arm/arm/cpufunc.c            |  73 ++++++++++++++++++++++++++++++++++-
 sys/arch/arm/arm/cpufunc_asm_xscale.S |  63 +++++++++++++++++++++++++++++-
 2 files changed, 133 insertions(+), 3 deletions(-)

diffs (171 lines):

diff -r 29e9e168f97d -r 478459480139 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Mon Nov 26 21:44:53 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Mon Nov 26 22:26:44 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.17 2001/11/23 19:17:04 thorpej Exp $     */
+/*     $NetBSD: cpufunc.c,v 1.18 2001/11/26 22:26:44 thorpej Exp $     */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -625,6 +625,74 @@
 
        xscale_setup                    /* cpu setup            */
 };
+
+struct cpu_functions xscale_writethrough_cpufuncs = {
+       /* CPU functions */
+       
+       cpufunc_id,                     /* id                   */
+       xscale_cpwait,                  /* cpwait               */
+
+       /* MMU functions */
+
+       xscale_control,                 /* control              */
+       cpufunc_domains,                /* domain               */
+       xscale_setttb,                  /* setttb               */
+       cpufunc_faultstatus,            /* faultstatus          */
+       cpufunc_faultaddress,           /* faultaddress         */
+
+       /* TLB functions */
+
+       armv4_tlb_flushID,              /* tlb_flushID          */
+       xscale_tlb_flushID_SE,          /* tlb_flushID_SE       */
+       armv4_tlb_flushI,               /* tlb_flushI           */
+       (void *)armv4_tlb_flushI,       /* tlb_flushI_SE        */
+       armv4_tlb_flushD,               /* tlb_flushD           */
+       armv4_tlb_flushD_SE,            /* tlb_flushD_SE        */
+
+       /* Cache functions */
+
+       xscale_cache_flushID,           /* cache_flushID        */
+       (void *)xscale_cache_flushID,   /* cache_flushID_SE     */
+       xscale_cache_flushI,            /* cache_flushI         */
+       (void *)xscale_cache_flushI,    /* cache_flushI_SE      */
+       xscale_cache_flushD,            /* cache_flushD         */
+       xscale_cache_flushD_SE,         /* cache_flushD_SE      */
+
+       cpufunc_nullop,                 /* cache_cleanID        s*/
+       (void *)cpufunc_nullop,         /* cache_cleanID_E      s*/
+       cpufunc_nullop,                 /* cache_cleanD         s*/
+       (void *)cpufunc_nullop,         /* cache_cleanD_E       */
+
+       xscale_cache_flushID,           /* cache_purgeID        s*/
+       (void *)xscale_cache_flushID,   /* cache_purgeID_E      s*/
+       xscale_cache_flushD,            /* cache_purgeD         s*/
+       xscale_cache_flushD_SE,         /* cache_purgeD_E       s*/
+
+       /* Other functions */
+
+       cpufunc_nullop,                 /* flush_prefetchbuf    */
+       armv4_drain_writebuf,           /* drain_writebuf       */
+       cpufunc_nullop,                 /* flush_brnchtgt_C     */
+       (void *)cpufunc_nullop,         /* flush_brnchtgt_E     */
+
+       (void *)cpufunc_nullop,         /* sleep                */
+
+       /* Soft functions */
+
+       xscale_cache_flushI,            /* cache_syncI          */
+       (void *)cpufunc_nullop,         /* cache_cleanID_rng    */
+       (void *)cpufunc_nullop,         /* cache_cleanD_rng     */
+       xscale_cache_flushID_rng,       /* cache_purgeID_rng    */
+       xscale_cache_flushD_rng,        /* cache_purgeD_rng     */
+       xscale_cache_flushI_rng,        /* cache_syncI_rng      */
+
+       cpufunc_null_fixup,             /* dataabt_fixup        */
+       cpufunc_null_fixup,             /* prefetchabt_fixup    */
+
+       xscale_context_switch,          /* context_switch       */
+
+       xscale_setup                    /* cpu setup            */
+};
 #endif /* CPU_XSCALE */
 
 /*
@@ -706,7 +774,8 @@
 #endif /* CPU_SA110 */
 #ifdef CPU_XSCALE
        if (cputype == CPU_ID_I80200) {
-               cpufuncs = xscale_cpufuncs;
+               pte_cache_mode = PT_C;  /* Select write-through cacheing. */
+               cpufuncs = xscale_writethrough_cpufuncs;
                cpu_reset_needs_v4_MMU_disable = 1;     /* XScale needs it */
                return 0;
        }
diff -r 29e9e168f97d -r 478459480139 sys/arch/arm/arm/cpufunc_asm_xscale.S
--- a/sys/arch/arm/arm/cpufunc_asm_xscale.S     Mon Nov 26 21:44:53 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_xscale.S     Mon Nov 26 22:26:44 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_xscale.S,v 1.6 2001/11/26 18:09:08 thorpej Exp $   */
+/*     $NetBSD: cpufunc_asm_xscale.S,v 1.7 2001/11/26 22:26:45 thorpej Exp $   */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -428,6 +428,67 @@
 
        mov     pc, lr
 
+/* Used in write-through mode. */
+ENTRY(xscale_cache_flushID_rng)
+       cmp     r1, #0x4000
+       bcs     _C_LABEL(xscale_cache_flushID)
+
+       and     r2, r0, #0x1f
+       add     r1, r1, r2
+       bic     r0, r0, #0x1f
+
+1:     mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
+       mcr     p15, 0, r0, c7, c5, 1   /* flush I cache single entry */
+       add     r0, r0, #32
+       subs    r1, r1, #32
+       bpl     1b
+
+       mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
+
+       CPWAIT(r0)
+
+       mov     pc, lr
+
+/* Used in write-though mode. */
+ENTRY(xscale_cache_flushD_rng)
+       cmp     r1, #0x4000
+       bcs     _C_LABEL(xscale_cache_flushD)
+
+       and     r2, r0, #0x1f
+       add     r1, r1, r2
+       bic     r0, r0, #0x1f
+
+1:     mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
+       add     r0, r0, #32
+       subs    r1, r1, #32
+       bpl     1b
+
+       mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
+
+       CPWAIT(r0)
+
+       mov     pc, lr
+
+/* Used in write-through mode. */
+ENTRY(xscale_cache_flushI_rng)
+       cmp     r1, #0x4000
+       bcs     _C_LABEL(xscale_cache_flushI)
+
+       and     r2, r0, #0x1f
+       add     r1, r1, r2
+       bic     r0, r0, #0x1f
+
+1:     mcr     p15, 0, r0, c7, c5, 1   /* flush I cache single entry */
+       add     r0, r0, #32
+       subs    r1, r1, #32
+       bpl     1b
+
+       mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
+
+       CPWAIT(r0)
+
+       mov     pc, lr
+
 /*
  * Context switch.
  *