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[src/trunk]: src/sys/arch/arm Add support for the Intel PXA210 and PXA250. F...
details: https://anonhg.NetBSD.org/src/rev/3b6a802decec
branches: trunk
changeset: 526395:3b6a802decec
user: thorpej <thorpej%NetBSD.org@localhost>
date: Fri May 03 03:28:48 2002 +0000
description:
Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
diffstat:
sys/arch/arm/arm/cpufunc.c | 29 ++++++++++++++++++++++-------
sys/arch/arm/arm32/cpu.c | 19 ++++++++++++++++---
sys/arch/arm/include/cpuconf.h | 11 +++++++----
sys/arch/arm/include/cpufunc.h | 9 +++++----
4 files changed, 50 insertions(+), 18 deletions(-)
diffs (219 lines):
diff -r 4ce4d65ffd72 -r 3b6a802decec sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Fri May 03 02:43:19 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Fri May 03 03:28:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.42 2002/04/12 21:52:45 thorpej Exp $ */
+/* $NetBSD: cpufunc.c,v 1.43 2002/05/03 03:28:48 thorpej Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -498,7 +498,8 @@
};
#endif /* CPU_SA110 */
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
struct cpu_functions xscale_cpufuncs = {
/* CPU functions */
@@ -553,7 +554,7 @@
xscale_setup /* cpu setup */
};
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
/*
* Global constants also used by locore.s
@@ -564,7 +565,8 @@
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
- defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
static void get_cachetype_cp15 __P((void));
static void
@@ -858,6 +860,16 @@
return 0;
}
#endif /* CPU_XSCALE_80321 */
+#ifdef CPU_XSCALE_PXA2X0
+ if (cputype == CPU_ID_PXA250 || cputype == CPU_ID_PXA210) {
+ cpufuncs = xscale_cpufuncs;
+
+ cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
+ get_cachetype_cp15();
+ pmap_pte_init_xscale();
+ return 0;
+ }
+#endif /* CPU_XSCALE_PXA2X0 */
/*
* Bzzzz. And the answer was ...
*/
@@ -1227,7 +1239,8 @@
#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
defined(CPU_ARM8) || defined (CPU_ARM9) || defined(CPU_SA110) || \
- defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
#define IGN 0
#define OR 1
@@ -1579,7 +1592,8 @@
}
#endif /* CPU_SA110 */
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
struct cpu_option xscale_options[] = {
#ifdef COMPAT_12
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
@@ -1620,6 +1634,7 @@
| CPU_CONTROL_CPCLK;
cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl);
+cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -1641,4 +1656,4 @@
__asm ("mcr p15, 0, %0, c1, c0, 1" :: "r" (0));
#endif
}
-#endif /* CPU_XSCALE_80200 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
diff -r 4ce4d65ffd72 -r 3b6a802decec sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c Fri May 03 02:43:19 2002 +0000
+++ b/sys/arch/arm/arm32/cpu.c Fri May 03 03:28:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.34 2002/05/02 22:57:36 rjs Exp $ */
+/* $NetBSD: cpu.c,v 1.35 2002/05/03 03:28:49 thorpej Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -45,7 +45,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.34 2002/05/02 22:57:36 rjs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.35 2002/05/03 03:28:49 thorpej Exp $");
#include <sys/systm.h>
#include <sys/malloc.h>
@@ -206,6 +206,13 @@
"rev 12", "rev 13", "rev 14", "rev 15",
};
+static const char *pxa2x0_steppings[16] = {
+ "step A-0", "step A-1", "step B-0", "step B-1",
+ "rev 4", "rev 5", "rev 6", "rev 7",
+ "rev 8", "rev 9", "rev 10", "rev 11",
+ "rev 12", "rev 13", "rev 14", "rev 15",
+};
+
struct cpuidtab {
u_int32_t cpuid;
enum cpu_class cpu_class;
@@ -277,6 +284,11 @@
{ CPU_ID_80321, CPU_CLASS_XSCALE, "i80321",
xscale_steppings },
+ { CPU_ID_PXA250, CPU_CLASS_XSCALE, "PXA250",
+ pxa2x0_steppings },
+ { CPU_ID_PXA210, CPU_CLASS_XSCALE, "PXA210",
+ pxa2x0_steppings }, /* XXX */
+
{ CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022ES",
generic_steppings },
@@ -450,7 +462,8 @@
#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
case CPU_CLASS_SA1:
#endif
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
case CPU_CLASS_XSCALE:
#endif
break;
diff -r 4ce4d65ffd72 -r 3b6a802decec sys/arch/arm/include/cpuconf.h
--- a/sys/arch/arm/include/cpuconf.h Fri May 03 02:43:19 2002 +0000
+++ b/sys/arch/arm/include/cpuconf.h Fri May 03 03:28:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuconf.h,v 1.1 2002/04/12 18:50:29 thorpej Exp $ */
+/* $NetBSD: cpuconf.h,v 1.2 2002/05/03 03:28:49 thorpej Exp $ */
/*
* Copyright (c 2002 Wasabi Systems, Inc.
@@ -54,7 +54,8 @@
defined(CPU_SA110) + defined(CPU_SA1100) + \
defined(CPU_SA1110) + \
defined(CPU_XSCALE_80200) + \
- defined(CPU_XSCALE_80321))
+ defined(CPU_XSCALE_80321) + \
+ defined(CPU_XSCALE_PXA2X0))
#else
#define CPU_NTYPES 2
#endif /* _KERNEL_OPT */
@@ -85,7 +86,8 @@
#endif
#if !defined(_KERNEL_OPT) || \
- (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
+ (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0))
#define ARM_ARCH_5 1
#else
#define ARM_ARCH_5 0
@@ -125,7 +127,8 @@
#endif
#if !defined(_KERNEL_OPT) || \
- (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
+ (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0))
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0
diff -r 4ce4d65ffd72 -r 3b6a802decec sys/arch/arm/include/cpufunc.h
--- a/sys/arch/arm/include/cpufunc.h Fri May 03 02:43:19 2002 +0000
+++ b/sys/arch/arm/include/cpufunc.h Fri May 03 03:28:48 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.21 2002/04/12 18:50:29 thorpej Exp $ */
+/* $NetBSD: cpufunc.h,v 1.22 2002/05/03 03:28:49 thorpej Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@@ -291,7 +291,7 @@
#endif
#if defined(CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE_80200) || \
- defined(CPU_XSCALE_80321)
+ defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_PXA2X0)
void armv4_tlb_flushID __P((void));
void armv4_tlb_flushI __P((void));
void armv4_tlb_flushD __P((void));
@@ -333,7 +333,8 @@
void sa110_setup __P((char *string));
#endif /* CPU_SA110 */
-#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
+#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_XSCALE_PXA2X0)
void xscale_cpwait __P((void));
void xscale_cpu_sleep __P((int mode));
@@ -375,7 +376,7 @@
void xscale_context_switch __P((void));
void xscale_setup __P((char *string));
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 */
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
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