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[src/trunk]: src/sys/arch/mips/mips Add support for MIPS32 and MIPS64 archite...
details: https://anonhg.NetBSD.org/src/rev/a18a04c79d35
branches: trunk
changeset: 523160:a18a04c79d35
user: simonb <simonb%NetBSD.org@localhost>
date: Tue Mar 05 15:53:00 2002 +0000
description:
Add support for MIPS32 and MIPS64 architectures:
- Use a table-driven CPU detection algorithm instead of multiple
case statements.
- Add MIPS32/64 feature detection using the architected CP0 registers
(from Broadcom Corp).
- Call MD mips_machdep_cache_config() function if
__HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
L2 cache on some ports.
diffstat:
sys/arch/mips/mips/mips_machdep.c | 973 +++++++++++++++++++++++++++----------
1 files changed, 702 insertions(+), 271 deletions(-)
diffs (truncated from 1259 to 300 lines):
diff -r f6faedb6e90a -r a18a04c79d35 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Tue Mar 05 15:50:59 2002 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Tue Mar 05 15:53:00 2002 +0000
@@ -1,4 +1,72 @@
-/* $NetBSD: mips_machdep.c,v 1.121 2002/01/30 16:10:08 uch Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.122 2002/03/05 15:53:00 simonb Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright 2000, 2001
+ * Broadcom Corporation. All rights reserved.
+ *
+ * This software is furnished under license and may be used and copied only
+ * in accordance with the following terms and conditions. Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * modified or unmodified copies of this software in source and/or binary
+ * form. No title or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and
+ * retain this copyright notice and list of conditions as they appear in
+ * the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of
+ * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any
+ * trademark or logo of Broadcom Corporation may be used to endorse or
+ * promote products derived from this software without the prior written
+ * permission of Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -52,11 +120,11 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.121 2002/01/30 16:10:08 uch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.122 2002/03/05 15:53:00 simonb Exp $");
+#include "opt_cputype.h"
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
-#include "opt_cputype.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -79,56 +147,253 @@
#include <uvm/uvm_extern.h>
#include <mips/cache.h>
-#include <mips/regnum.h> /* symbolic register indices */
+#include <mips/regnum.h>
#include <mips/locore.h>
#include <mips/psl.h>
#include <mips/pte.h>
-#include <machine/cpu.h> /* declaration of of cpu_id */
+#include <machine/cpu.h>
+
+#if defined(MIPS32) || defined(MIPS64)
+#include <mips/mipsNN.h> /* MIPS32/MIPS64 registers */
+#endif
/* Internal routines. */
-int cpu_dumpsize __P((void));
-u_long cpu_dump_mempagecnt __P((void));
-int cpu_dump __P((void));
+int cpu_dumpsize(void);
+u_long cpu_dump_mempagecnt(void);
+int cpu_dump(void);
-#ifdef MIPS1
-static void mips1_vector_init __P((void));
+#if defined(MIPS1)
+static void mips1_vector_init(void);
+extern long *mips1_locoresw[];
#endif
#if defined(MIPS3)
#if defined(MIPS3_5900)
-extern void r5900_vector_init(void);
+static void r5900_vector_init(void);
#else
-static void mips3_vector_init __P((void));
+static void mips3_vector_init(void);
+#endif
+extern long *mips3_locoresw[];
#endif
+
+#if defined(MIPS32)
+static void mips32_vector_init(void);
+extern long *mips32_locoresw[];
+#endif
+
+#if defined(MIPS64)
+static void mips64_vector_init(void);
+extern long *mips64_locoresw[];
#endif
mips_locore_jumpvec_t mips_locore_jumpvec;
long *mips_locoresw[3];
-extern long *mips1_locoresw[]; /* locore_mips1.S */
-extern long *mips3_locoresw[]; /* locore_mips3.S */
int cpu_arch;
int cpu_mhz;
int mips_num_tlb_entries;
+int mips_cpu_flags;
+int mips_has_llsc;
+int mips_has_r4k_mmu;
+int mips3_pg_cached;
struct user *proc0paddr;
struct proc *fpcurproc;
struct pcb *curpcb;
struct segtab *segbase;
-
caddr_t msgbufaddr;
#ifdef MIPS3_4100 /* VR4100 core */
int default_pg_mask = 0x00001800;
#endif
+struct pridtab {
+ int cpu_cid;
+ int cpu_pid;
+ int cpu_rev; /* -1 == wildcard */
+ int cpu_isa; /* -1 == probed (mips32/mips64) */
+ int cpu_ntlb; /* -1 == unknown, 0 == probed */
+ int cpu_flags;
+ char *cpu_name;
+};
+
+/*
+ * Assumptions:
+ * - All MIPS3+ have an r4k-style MMU. _Many_ assumptions throughout
+ * much of the mips code about this. Includes overloaded usage of
+ * MIPS3_PLUS.
+ * - All MIPS3+ use the same exception model (cp0 status, cause bits,
+ * etc). _Many_ assumptions throughout much of the mips code about
+ * this. Includes overloaded usage of MIPS3_PLUS.
+ * - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h>
+ * will need to be revised if this is false.
+ */
+#define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV
+#define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */
+
+static const struct pridtab *mycpu;
+
+static const struct pridtab cputab[] = {
+ { 0, MIPS_R2000, -1, CPU_ARCH_MIPS1, 64,
+ 0, "MIPS R2000 CPU" },
+ { 0, MIPS_R3000, MIPS_REV_R3000, CPU_ARCH_MIPS1, 64,
+ 0, "MIPS R3000 CPU" },
+ { 0, MIPS_R3000, MIPS_REV_R3000A, CPU_ARCH_MIPS1, 64,
+ 0, "MIPS R3000A CPU" },
+ { 0, MIPS_R6000, -1, CPU_ARCH_MIPS2, 32,
+ MIPS_NOT_SUPP, "MIPS R6000 CPU" },
+
+ /*
+ * rev 0x00 and 0x30 are R4000, 0x40 and 0x50 are R4400.
+ * should we allow ranges and use 0x00 - 0x3f for R4000 and
+ * 0x40 - 0xff for R4400?
+ */
+ { 0, MIPS_R4000, MIPS_REV_R4000_A, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "MIPS R4000 CPU" },
+ { 0, MIPS_R4000, MIPS_REV_R4000_B, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "MIPS R4000 CPU" },
+ { 0, MIPS_R4000, MIPS_REV_R4400_A, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "MIPS R4400 CPU" },
+ { 0, MIPS_R4000, MIPS_REV_R4400_B, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "MIPS R4400 CPU" },
+
+ { 0, MIPS_R3LSI, -1, CPU_ARCH_MIPS1, -1,
+ MIPS_NOT_SUPP, "LSI Logic R3000 derivative" },
+ { 0, MIPS_R6000A, -1, CPU_ARCH_MIPS2, 32,
+ MIPS_NOT_SUPP, "MIPS R6000A CPU" },
+ { 0, MIPS_R3IDT, -1, CPU_ARCH_MIPS1, -1,
+ MIPS_NOT_SUPP, "IDT R3041 or RC36100 CPU" },
+ { 0, MIPS_R4100, -1, CPU_ARCH_MIPS3, 32,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, "NEC VR4100 CPU" },
+ { 0, MIPS_R4200, -1, CPU_ARCH_MIPS3, -1,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR4200 CPU" },
+ { 0, MIPS_R4300, -1, CPU_ARCH_MIPS3, 32,
+ CPU_MIPS_R4K_MMU, "NEC VR4300 CPU" },
+ { 0, MIPS_R4600, -1, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "QED R4600 Orion CPU" },
+ { 0, MIPS_R4700, -1, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "QED R4700 Orion CPU" },
+
+ { 0, MIPS_R8000, -1, CPU_ARCH_MIPS4, 384,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R8000 Blackbird/TFP CPU" },
+ { 0, MIPS_R10000, -1, CPU_ARCH_MIPS4, 64,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R10000 CPU" },
+ { 0, MIPS_R12000, -1, CPU_ARCH_MIPS4, 64,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R12000 CPU" },
+ { 0, MIPS_R14000, -1, CPU_ARCH_MIPS4, 64,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R14000 CPU" },
+
+ /* XXX
+ * If the Processor Revision ID of the 4650 isn't 0, the following
+ * entry needs to be adjusted. Can't use a wildcard match because
+ * the TX39 series processors share the same Processor ID value.
+ * Or maybe put TX39 CPUs first if the revid doesn't overlap with
+ * the 4650...
+ */
+ { 0, MIPS_R4650, 0, CPU_ARCH_MIPS3, -1,
+ MIPS_NOT_SUPP /* no MMU! */, "QED R4650 CPU" },
+ { 0, MIPS_TX3900, MIPS_REV_TX3912, CPU_ARCH_MIPS1, 32,
+ 0, "Toshiba TX3912 CPU" },
+ { 0, MIPS_TX3900, MIPS_REV_TX3922, CPU_ARCH_MIPS1, 64,
+ 0, "Toshiba TX3922 CPU" },
+ { 0, MIPS_TX3900, MIPS_REV_TX3927, CPU_ARCH_MIPS1, 64,
+ 0, "Toshiba TX3927 CPU" },
+ { 0, MIPS_R5000, -1, CPU_ARCH_MIPS4, 48,
+ CPU_MIPS_R4K_MMU, "MIPS R5000 CPU" },
+ { 0, MIPS_RM5200, -1, CPU_ARCH_MIPS4, 48,
+ CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV, "QED RM5200 CPU" },
+
+ /* XXX
+ * The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See
+ * "Migrating to the RM7000 from other MIPS Microprocessors"
+ * for more details.
+ */
+ { 0, MIPS_RM7000, -1, CPU_ARCH_MIPS4, 48,
+ MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV, "QED RM7000 CPU" },
+
+ /*
+ * IDT RC32300 core is a 32 bit MIPS2 processor with
+ * MIPS3/MIPS4 extensions. It has an R4000-style TLB,
+ * while all registers are 32 bits and any 64 bit
+ * instructions like ld/sd/dmfc0/dmtc0 are not allowed.
+ *
+ * note that the Config register has a non-standard base
+ * for IC and DC (2^9 instead of 2^12).
+ *
+ */
+ { 0, MIPS_RC32300, -1, CPU_ARCH_MIPS3, 16,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32300 CPU" },
+ { 0, MIPS_RC32364, -1, CPU_ARCH_MIPS3, 16,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32364 CPU" },
+ { 0, MIPS_RC64470, -1, CPU_ARCH_MIPSx, -1,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC64474/RC64475 CPU" },
+
+ { 0, MIPS_R5400, -1, CPU_ARCH_MIPSx, -1,
+ MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR5400 CPU" },
+ { 0, MIPS_R5900, -1, CPU_ARCH_MIPS3, 48,
+ CPU_MIPS_R4K_MMU, "Toshiba R5900 CPU" },
+
+#if 0 /* ID collisions : can we use a CU1 test or similar? */
+ { 0, MIPS_R3SONY, -1, CPU_ARCH_MIPS1, -1,
+ MIPS_NOT_SUPP, "SONY R3000 derivative" }, /* 0x21; crash R4700? */
+ { 0, MIPS_R3NKK, -1, CPU_ARCH_MIPS1, -1,
+ MIPS_NOT_SUPP, "NKK R3000 derivative" }, /* 0x23; crash R5000? */
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