[src/netbsd-1-6]: src/sys/dev/pci Pull up revision 1.13 (requested by bouyer ...

[tron <tron%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e375aff84659
branches:  netbsd-1-6
changeset: 531352:e375aff84659
user:      tron <tron%NetBSD.org@localhost>
date:      Wed May 26 14:02:23 2004 +0000

description:
Pull up revision 1.13 (requested by bouyer in ticket #1698):
Use the bus_space_*_stream_* methods to access the chip's registers.
As we turn the chip to big-endian mode on big-endian systems, we should
never byte-swap the data read/written from/to registers. Tested on sparc64.
Finally fix kern/13341 by Jason R. Thorpe (really, the hard work of putting
bus_dmamap_sync() calls at the right places has been done my Jason mid-2001 :)

diffstat:

 sys/dev/pci/if_tireg.h |  13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diffs (34 lines):

diff -r f333a9e38a6d -r e375aff84659 sys/dev/pci/if_tireg.h
--- a/sys/dev/pci/if_tireg.h    Wed May 26 14:00:59 2004 +0000
+++ b/sys/dev/pci/if_tireg.h    Wed May 26 14:02:23 2004 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_tireg.h,v 1.11 2001/06/30 17:53:59 bjh21 Exp $ */
+/* $NetBSD: if_tireg.h,v 1.11.16.1 2004/05/26 14:02:23 tron Exp $ */
 
 /*
  * Copyright (c) 1997, 1998, 1999
@@ -966,13 +966,24 @@
 /*
  * Register access macros. The Tigon always uses memory mapped register
  * accesses and all registers must be accessed with 32 bit operations.
+ * The Tigon can operate in big-endian mode, so we always write to the
+ * registers in native byte order. We assume that all big-endian hosts
+ * with a PCI bus have __BUS_SPACE_HAS_STREAM_METHODS defined.
  */
 
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+#define CSR_WRITE_4(sc, reg, val)      \
+       bus_space_write_stream_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
+
+#define CSR_READ_4(sc, reg)            \
+       bus_space_read_stream_4(sc->ti_btag, sc->ti_bhandle, (reg))
+#else
 #define CSR_WRITE_4(sc, reg, val)      \
        bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
 
 #define CSR_READ_4(sc, reg)            \
        bus_space_read_4(sc->ti_btag, sc->ti_bhandle, (reg))
+#endif
 
 #define TI_SETBIT(sc, reg, x)  \
        CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x)))