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[src/trunk]: src/sys/arch/mips TX39, R5900 cache configuration.
details: https://anonhg.NetBSD.org/src/rev/88d832cc3650
branches: trunk
changeset: 518595:88d832cc3650
user: uch <uch%NetBSD.org@localhost>
date: Sun Dec 02 10:37:25 2001 +0000
description:
TX39, R5900 cache configuration.
diffstat:
sys/arch/mips/conf/files.mips | 13 ++++++++-----
sys/arch/mips/include/r3900regs.h | 4 +++-
2 files changed, 11 insertions(+), 6 deletions(-)
diffs (50 lines):
diff -r b2781d8d22e0 -r 88d832cc3650 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Sun Dec 02 10:36:33 2001 +0000
+++ b/sys/arch/mips/conf/files.mips Sun Dec 02 10:37:25 2001 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.35 2001/11/28 10:21:16 lukem Exp $
+# $NetBSD: files.mips,v 1.36 2001/12/02 10:37:25 uch Exp $
#
defflag opt_cputype.h NOTYET # MIPS1 MIPS2 MIPS3 MIPS4 MIPS5
@@ -14,10 +14,13 @@
MIPS3_NO_PV_UNCACHED
file arch/mips/mips/cache.c
-file arch/mips/mips/cache_r3k.c mips1
-file arch/mips/mips/cache_r3k_subr.S mips1
-file arch/mips/mips/cache_r4k.c mips3
-file arch/mips/mips/cache_r5k.c mips3
+file arch/mips/mips/cache_r3k.c mips1
+file arch/mips/mips/cache_r3k_subr.S mips1
+file arch/mips/mips/cache_tx39.c mips1 & enable_mips_tx3900
+file arch/mips/mips/cache_tx39_subr.S mips1 & enable_mips_tx3900
+file arch/mips/mips/cache_r4k.c mips3
+file arch/mips/mips/cache_r5k.c mips3
+file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
file arch/mips/mips/db_disasm.c ddb
file arch/mips/mips/db_interface.c ddb | kgdb
diff -r b2781d8d22e0 -r 88d832cc3650 sys/arch/mips/include/r3900regs.h
--- a/sys/arch/mips/include/r3900regs.h Sun Dec 02 10:36:33 2001 +0000
+++ b/sys/arch/mips/include/r3900regs.h Sun Dec 02 10:37:25 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: r3900regs.h,v 1.4 2000/08/24 05:31:59 uch Exp $ */
+/* $NetBSD: r3900regs.h,v 1.5 2001/12/02 10:37:25 uch Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -56,11 +56,13 @@
* R3900 don't have PE, CM, PZ, SwC and IsC.
*/
#define R3900_SR_NMI 0x00100000 /* r3k PE position */
+#if 0
#undef MIPS1_PARITY_ERR
#undef MIPS1_CACHE_MISS
#undef MIPS1_PARITY_ZERO
#undef MIPS1_SWAP_CACHES
#undef MIPS1_ISOL_CACHES
+#endif
/*
* [context register]
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